JETWAY V6DP User Manual

JETWAY V6DP User Manual Manual pdf 27 page image

24Please refer to section 3-6-1AGP Timing SettingsPlease refer to section 3-6-2PCI Timing SettingsPlease refer to section 3-6-3System BIOS CacheableSelecting Enabled allows caching of the system BIOS ROM at F0000h-FFFFFh, resulting inbetter system performance. However, if any program writes to this memory area, a systemerror may result. The settings are: Enabled and Disabled.Video RAM CacheableSelect Enabled allows caching of the video BIOS, resulting in better system performance.However, if any program writes to this memory area, a system error may result. The settingsare: Enabled and Disabled.Memory HoleYou can reserve this area of system memory for ISA adapter ROM. When this area isreserved, it cannot be cached. The user information of peripherals that need to use this area ofsystem memory usually discusses their memory requirements. The settings are: Enabled andDisabled.3-6-1 DRAM Timing SettingsCMOS Setup Utility – Copyright(C) 1984-2003 Award SoftwareDRAM Timing SettingsItem HelpAuto Configuration OptimizedRAS Active Time 6TRAS Precharge Time 3TRAS to CAS Delay 3TCAS Latency 2.5TBank Interleave 4 BankDRAM Queue Depth 4 LevelDRAM Command Rate 2T CommandMenu Level >>↑↓→← Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General HelpF5:Previous Values F6:Optimized Defaults F7:Standard DefaultsRAS Active TimeThis field let’s you insert a timing delay between the CAS and RAS strobe signals, used whenDRAM is written to, read from, or refreshed. Fast gives faster performance; and Slow givesmore stable performance. This field applies only when synchronous DRAM is installed in thesystem. The settings are: 2T and 3T.RAS Precharge Time