DVR-6100/6100K8CIRCUIT DESCRIPTIONNo. Pin Name I/O Description6 DSP A. BOOST O DSP auto boot.7 H/P CHK I Detection pin of headphones jack.8 CS8415A-CE O DIR IC (IC39) chip enable.9 EMPHASIS O CS4228 DAC IC emphasis ON/OFF0 TUNED I Tuned signal input for tuner.1 DSP INTREQ O DSP INT request.2 4094CE O 4049 (IC81)chip enable.3 CS49326 CE O CS49326 DSP IC (IC33) chip enable.4 CS4228 CE O CS4228 DAC IC (IC31) chip enable.5 DSP CLK O CS49326 DSP IC (IC33) clock output.6 CS49326 DATA IN I CS49326 DSP IC (IC33) data input.7 DSP DA OUT O CS49326 DSP IC (IC33) data output.8 VREF I A/D reference voltage input.9 PROTECT I AMP protection input.0 KEY IN I A/D key input.1 EEPROM DATA I/O EEPROM (IC52) data output.2 KEY2 IN I A/D key input.3 8415 DA IN I CS8415 DIR IC (IC39) data input.4 DVD OPTION I Setting pin for the destination.5 PLL DATA IN I PLL data input.6 STEP OPTION I Setting pin for tuner destination.7 VSS(G) I Analog ground.8 RST I Reset signal input.9 EXTAL I Crystal resonator (10MHz) connection.0 XTAL O Crystal resonator (10MHz) connection.1 GND - Digital ground.2 NC O Unused.3 GND - GND4 VDD I Digital ground.5 VFDP I Power supply for VFDP.6 STANDBY O Control pin for power relay on/off.7 SPK RELAY O Control pin for speaker relay on/off.8 SUB ON/OFF O Gain control for sub woofer.9 CS8415 RST O CS8415 (IC39) reset signal output.0 PLL CE O PLL chip enable.1 PLL CLK O PLL clock output.2 PLL D OUT O PLL data output.3 A CLK O Common clock (LC7821,BU4094) output.4 A DATA O Common data (LC7821,BU4094) output.5 EEPROM CLK O EEPROM (IC52) clock output.59 VIDEO (SW1~SW4) O Control pin for video.0 4228 RST O CS4228 (IC31) reset signal output.1 LC7821 CE O LC7821(tuner pack) chip enable.2 SM7346 CE O Volume IC (Main IC11) chip enable.3 T MUTE O Tuner mute control.4 S MUTE O Mute control pin for surround signal5 C MUTE O Mute control pin for center signal.6 F MUTE O Mute control pin for front signal.7 W MUTE O Mute control pin for sub woofer signal.8 CS49326 RST O CS49326 DSP IC (IC5) reset signal output.71 DSP (A15~A17) O DSP ROM address (SEL 1~3).88 SEG (1~17) O FIP segment output.9 VDD - Digital power supply.,91 SEG18,19 O FIP segment output.100 GRID (11~3) O FIP Grid output.