Kenwood NX-720 Service Manual

Also see for NEXEDGE NX-720: Installation guide Instruction manual Technical details Service manual Instruction manual

Contents

NX-720(G)/72013Fig. 6 PLL circuitCIRCUIT DESCRIPTION5. PLL Frequency Synthesizer5-1. TCXO (X1)The TCXO (X1) generates a reference frequency of16.8MHz for the PLL frequency synthesizer. This referencefrequency is applied to pin 9 of the PLL IC (IC2) and is con-nected to the IF circuit as a 2nd local signal through the Tri-pler.The frequency adjustment is achieved by switching theratio of the dividing frequency. The resolution of the adjustingfrequency is approximately 4Hz.5-2. VCOThere is an RX VCO and a TX VCO.The TX VCO (Q7) generates a transmit carrier and theRX VCO (Q6) generates the 1st local signal. For the VCOoscillation frequency, the transmit carrier is 136 to 174 MHzand the 1st local signal is 185.95 to 223.95MHz.The VCO oscillation frequency is determined by one sys-tem of operation switching terminal "T/R" and two systemsof voltage control terminals "CV" and "ASSIST".The operation switching terminal, "T/R", is controlled bythe control line (/T_R) output from the ASIC (IC507). Whenthe /T_R logic is low, the VCO outputs the transmit carrierand when it is high, it outputs the 1st local receive signal.The voltage control terminals, "CV" and "ASSIST", arecontrolled by the PLL IC (IC2) and ASIC (IC507) and theoutput frequency changes continuously according to theapplied voltage. For the modulation input terminal, "VCO_MOD", the output frequency changes according to the ap-plied voltage. This is used to modulate the VCO output."VCO_MOD" works only when "/T_R" is low.5-3. PLL IC (IC2)The PLL IC compares the differences in phases of theVCO oscillation frequency and the TCXO reference fre-quency, returns the difference to the VCO CV terminal andrealizes the "Phase Locked Loop" for the return control. Thisallows the VCO oscillation frequency to accurately match(lock) the desired frequency.When the frequency is controlled by the PLL , the fre-quency convergence time increases as the frequency dif-ference increases when the set frequency is changed. Tosupplement this, the ASIC (IC507) is used before control bythe PLL IC to bring the VCO oscillation frequency close tothe desired frequency. As a result, the VCO CV voltage doesnot change and is always stable at approximately 2.5V.The desired frequency is set for the PLL IC by the ASIC(IC507) through the 3-line "SDO1", "P_SCK1", "/PCS_RF"serial bus. Whether the PLL IC is locked or not is monitoredby the ASIC through the “PLD” signal line. If the VCO is notthe desired frequency (unlocked), the "PLD" logic is low.The modulation signal of the Low-speed-Data is appliedto pin 23 of the PLL IC (IC2).The modulation signal that is digital data of a samplingfrequency of 96 kHz is set for the PLL IC by the DSP (IC502)through the “PLL_MOD” line.5-4. Local Switch (D16, D17)The connection destination of the signal output from thebuffer amplifi er (Q11) is changed with the diode switch (D17)that is controlled by the transmission power supply, HSW,and the diode switch (D16) that is controlled by the receptionpower supply, 50R. If the HSW logic is high, it is connectedto a transmit-side drive (Q102). If the HSW logic is low, it isconnected to a receive-side mixer (Q202).T/ RSWHSW50RD16,17BUFFAMPBUFFAMPQ11Q10VCOTX: Q7D5,8,11,12RX: Q6D4,7,9,10PLLLoopFilterVCO MODASSISTCVTCXOX1 16.8MHzSDO1PCK_RF/PCS RFPLLMODIC2IC3(2/2)IC3(1/2)50CS150Cto 1st MIXerto TX stageBPFDoublerQ5MODD15