Kenwood NXR-700 Service Manual

Also see for NEXEDGE NXR-700: Brochure Instruction manual Instruction manual Instruction manual Instruction manual

Contents

NXR-7007CIRCUIT DESCRIPTIONQ171/N1/RPD+5V+5V+9VQ3+5V208IC55FinLPFLPFQ16+9VLPFQ23+9VQ18REFin+9LV+9LV+9LV+9LVSW SWQ10SW SWQ11Q14Q59Q7195.95~209.95MHz (K)185.95~194.95MHz (K2)Q8209.95~223.95MHz (K)194.95~203.95MHz (K2)Div.ActiveLPFIC6 16 IC30ADC IC91/2IC33 10 IC30ADCQ2,4Q331/N1/RPD+5V+5V+9RQ22+5V208IC115FinLPFLPFLPFLPFLPFLPFQ38+5VQ21+5V+3VQ53+5VAQ35+5VDQ36REFinDiv.Div.ATTATTATTATTQ2499.0MHz2 749.5MHzFig. 2 Receiver PLL circuits2. Receiver PLL circuitsThe receiver unit (X55-309) has the 1st-PLL circuit forcontrolling the VCO that generates the hetero signal to thefirst local oscillator, and the 2nd-PLL circuit for controllingthe VCO that generates the hetero signal to the second lo-cal oscillator.The 1st-PLL circuit consists of the VCO (Q7 and Q8), theBuffer amplifier (Q17), the RF amplifiers (Q16 and Q3), thePLL-IC (IC5), the Active loop filters (Q2 and Q4) and theBand switches (Q14, Q10, Q11 and Q59). The signal inthe195.95 (K), 185.95 (K2) through under 209.95MHz (K),194.95MHz (K2) band generated by VCO Q7 and the 209.95(K), 194.95 (K2) through 223.95MHz (K), 203.95MHz (K2)band generated by VCO Q8 is input to IC5 (pin5) via Q17and Q16 as the Fin signal. The 6MHz reference signal gen-erated by the DDS-IC (IC7) is input to IC5 (pin8) via Q3. Twosignals, Fin and REFin, are phase-compared as the 100kHzcomparison frequency by each frequency divider. The VCOoutput with the frequency synchronized is input to the 1st-Mixer as the first local oscillator Upper hetero signal ap-proximately +17dBm via Q17, Q23, and Q18. The controlvoltage is input to IC30 (ADC) pin16 via IC6.Meanwhile, the 2nd-PLL circuit consists of the VCO (Q24),the Buffer amplifier (Q33), the RF amplifier (Q38, Q22), andthe PLL-IC (IC11). The 99.0MHz signal generated by Q24 isinput to IC11 (pin5) as the Fin signal via Q38. The 19.2MHzInternal reference clock distributed by the transmitter unit(X56-311) is input as the REFin signal to IC11 (pin8) via Q22.Two signals, Fin and REFin, are phase-compared by eachfrequency divider as the comparison frequency of 200kHz.The VCO output with the frequency synchronized is input toIC9 (prescaler IC) pin2 via Q33 and Q21. The 49.5MHz sig-nal is frequency-divided into halves by IC9 and is excited byQ53 and distributed. One is input to IC12 (pin1) via Bufferamplifier_Q35. The other is input to IC13 (pin4) via Bufferamplifier_Q36. Both are input as approximately -16dBm forthe second local oscillator Lower hetero signal. The controlvoltage at this point is input to IC30 (ADC) pin 10 via IC33.