TH-22A/AT/ECIRCUIT DESCRIPTIONPLL CIRCUITe PLLThe output from the 12.8 MHz reference oscillator consist-ing of X1 is divided by IC1 to produce a 5 kHz or 6.25 kHzreference frequency. The comparison frequency is obiainedby amplifying the VCO output by Q2 and dividing it by thePLL IC (1C1).5, 10, 12.5, 15, 20, and 25kHz PLL synthesizer is imple-mented by phase-comparing the reference frequency andcomparison frequency obtained when X71 is divided.The pulse output from pins 18 and 20 of IC1 according tothe difference between the reference frequency and thecomparison frequency is passed through the charge pump,and is changed to DC current by a low-pass filter to producethe lock voltage.The power supply of the charge pump is raised from 3Mby the DC-DC converter to increase the lock voltage to about7V.e VCO (X58-4090-00)The desired frequency is directly produced by the Colpittsoscillator configured around FET Q2. The lock voltage isapplied to varicap diodes D1 and D2 to change the oscillatorfrequency. The TX pin is made "L" during transmission. Q1and D4 are then turned off to change over the oscillationfrequency.IC4MB1511PFV-G-BND+V_X58-409:VC0 Tec +4] CLKT “| 13] DATAil | 14) EP, oure C2414 FIN osc IN art : ty VCO ro tN= i g - ; BUEFER Q3 RF AM zaif L Saa OUT5 t DRIVER OSC OUT }3 {é 5 73 ¥; MIXER ‘| PLLIC “ Lnx ULF DETECTION C2ae ge Cye-—-f from 1C206 . = 7V 3M18 LOS+ = If DC-DC converter ICm 20 sy ©)bids te!re ra a | |cvy MOD u*MIC AMPNy Ny Wr WyLo 4 Li, monLPFFig. 7 PLL and VCO circuits* Unlock detection circuit , 3C.When the PLL is in the unlock state, the pulse that is ict ®output to the UL pin (pin 8) of [C1 is waveform shaped by D3, 3 03 = JT LoLC9, R11, and C8. The UL pin is then made high. The voltage UL vf y-COMat the UL pin is monitored by the microprocessor to control ET 3}the transmission or reception selection timing. i) IFig. 8 Unlock detection circuit