Kenwood TK-3160 Service Manual

Also see for TK-3160: Service manual Specifications Instruction manual Instruction manual Specifications

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TK-31608CIRCUIT DESCRIPTION6) Tone Volume Fixed CircuitThis function generates a TONE signal sound even if theAF volume of the transceiver is the minimum.A TONE signal is sent through Q602 to the AF amplifierwhen, in the FPU, “TONE Volume Fixed” is set to ON.7) SquelchPart of the AF signal from the IC enters the FM IC (IC401)again, and the noise component is amplified and rectifiedby a filter and an amplifier to produce a DC voltagecorresponding to the noise level.The DC signal from the FM IC goes to the analog port ofthe microprocessor (IC805). IC805 determines whether tooutput sounds from the speaker by checking whether theinput voltage is higher or lower than the preset value.To output sounds from the speaker, IC805 sends a highsignal to the SP MUTE line and turns IC605 on throughQ603,Q604,Q607 and Q608. (See Fig. 5)8) Receive Signalling(1) QT/DQTThe output signal from IF IC (IC401) enters themicroprocessor (IC805) through IC601. IC805 determineswhether the QT or DQT matches the preset value, andcontrols the SP MUTE and the speaker output soundsaccording to the squelch results.(2) 2-TONEPart of the received AF signal output from the AF amplifierIC602, and then pass through an audio processor (IC601),goes to the other AF amplifier IC603, is compared, and thengoes to IC805. IC805 checks whether 2-TONE data isnecessary. If it matches, IC805 carries out a specifiedoperation, such as turning the speaker on. (See Fig. 5)(3) MSK (Fleet Sync)Fleet Sync utilizes 1200bps and 2400bps MSK signal isoutput from pin 6 of IC601. And is routed to the VCO.When encoding MSK, the microphone input signal is muted.(4) DTMFThe DTMF input signal from the IF IC (IC401) is amplifiedby IC602 and goes to IC601, the DTMF decoder. Thedecoded information is then processed by the CPU.3. PLL Frequency SynthesizerThe PLL circuit generates the first local oscillator signal forreception and the RF signal for transmission.1) PLLThe frequency step of the PLL circuit is 5 or 6.25kHz.A 16.8MHz reference an oscillator signal is divided at IC1by a fixed counter to produce oscillator (VCO) output signalwhich is buffer amplified by Q9 then divided in IC1 by adual-module programmable counter. The divided signal iscompared in phase with the 5 or 6.25kHz reference signalfrom the phase comparator in IC1. The output signal fromthe phase comparator is filtered through a low-pass filterand passed to the VCO to control the oscillatorfrequency.(See Fig. 6)2) VCOThe operating frequency is generated by Q6 in transmitmode and Q5 in receive mode. The oscillator frequency iscontrolled by applying the VCO control voltage, obtainedfrom the phase comparator, to the varactor diodes (D4 andD7 in transmit mode and D3 and D9 in receive mode). TheRX pin is set high in receive mode causing Q8 and Q12 toturn Q6 off and turn Q5 on.The TX pin is set high in transmit mode. The outputs fromQ5 and Q6 are amplified by Q9 and sent to the RF amplifiers.Fig. 4 Tone volume fixed circuitIC805CPUBEEPBEEPSWTONE VOL FIXEDIC601AQUA VOLIC605TA7368FQ602 Hi: ONLOW: OFF+SPSP-J[VOL Position vs Output Level]Output Level (mV)MinONOFF25500Center MaxFig. 5 AF amplifier and squelchRECEIVE SIGNALINGRECEIVE SIGNALINGSPQ608SWIF AmpFM IF IC401IC602IF AmpIC601IC605AF PAIC805IC603BPF & COMPALATER Q603,604,607SWQT/DQT2-TONEDTMFCLK,DATA,STD,LOADNSIGNALSP MUTEHSDILSDIAN SQLCPUAQUA