CIRCUIT DESECRIPTIONTM-2550A/E,2530APinNo. | Name |in/Out Function Logic |Pin No. | Name [In/Out Function Logic1 RDO | Encoder E1 33 P20 is) 1750Hz Tone Controt (T,W) IL2 RD1 | Encoder E2 34 P21 ie] PLL Enable Signal IL3 R40 1/0 | Data Bus (DO) 35 P22 O | HD61602 RE Signal LS4 R41 1/0 | Data Bus (D1) 36 P23 (o) HD61602 WR Signal “LY5 R42 1/0 | Data Bus (D2) 37 P30 fa) PLL (Tone) Data Output6 R43 1/0 | Data Bus (D3) 38 P31 (0) Squelch Control Signal TL7 R50 1/0 | Data Bus (D4) 39 P32 O | Audio Mute Signal a8 R51 1/O | Data Bus (D5) 40 P33 (0) PLL (Tone) Clock Output9 R52 1/0 Data Bus (D6) 41 RBO j VOICE SW Input LI10 R53 HO Data Bus (D7) 42 RB1 ) PHONE (K,M) SW input14 R60 \ HD61602 READY Signal “LD P.MR (T,W) SW input LI12 R61 | | SUB CPU Busy Signal IL) 43 RB2 ; MIC Down SW Input LE13 R62 { Busy Signal 44 RB3 ! MIC Up SW Input LS14 R63 \ Tone SW Input LP} 45 KOO ! SW Return (S1)15 R70 | 16 Key Return (K1) 46 KO1 | SW Return ($2)16 R71 { 16 Key Return (K2) 47 KO2 l SW Return (S3)17 R72 { 16 Key Return (K3) 48 KO3 ! SW Return (S4)18 R73 I 16 Key Return (K4) 49 RESET Reset Input LY19 RAO O __| Memory Lamp SI-L| 50 Xin Clock20 RA1 ie) RAM OD Signal Output 51 Xout Clock21 RA2 QO | Standby Signal Output ‘LF | 52. |ROLo Back up Information Input LST22 RA3 (e) RAM A8 Signal Output 53 R80 I SUB CPU Request Signal IL23 POd ie) Address Latch S7k 54 R81 t PTT SW Input LI24 PO1 ce) RAM CE Signal Output LA 55 R82 ! DCL Diode Matrix Input25 PO2 (e) HD61602 CS Signal Qutput LI | 56 R83 \ SCAN Timer Trigger pulse26 £03 ie) RAM CE2 Signal Output 57 R90 Oo Keyboard select27 P10 ie) 16 Key Scan (K5) 58 R91 0) Serial Data Output28 Pil ie] 16 Key Scan (K6) 59 R92 oO Serial Clock Output29 P12 O__| 16 Key Scan (K7) 60 RCO O LED (DCL) Control LST30 P13 ie) 16 Key Scan (K8) 61 RC1 io) LED (C.SQ) Control LI31 TEST GND 62 RC2 Oo SW Scan32 Vss GND 63 RC3 Oo Tone DATA LOAD Signal LST64 VDD Power SupplyTable 7. TMP47C46N-9042 Terminal functions (Control unit 1C2)Pin No. | Name |tn/Out Function Logic | PinNo. | Name [In/Out Function Logic:| OOUT Open 21 CL2 Clock2 P20 oO VS-1 PS4 22 INT1 ! Modem Clock Input3 P21 (@) “Beeper’ Switching 23 POO i] Backup Clock Input4 P22 (6) MAIN CPU Busy Signal STL 24 PO} ! Serial Clock Input5 P23 ie) VS-1 SR 25 PO2 Open6 P10 (e) Adress Latch SIL 26 PO3 | Serial Data Input7 Pit 27 P6O 1/0 | Modem Data Input/Output8 P12 i HD61602 READY Signal SILI 28 P61 e) Modem Me Signal Output9 P13 O | VS-1 BY JL] 2 P62 O | MAIN CPU Request Signal STL10 P30 ie) VS-1 PSO 30 P63 oO RAM A8 Signal Output11 P31 (es) VS-1 PS1 31 P50 1/0 |DATA BUS (DO)12 P32 oO VS-1 PS2 32 P51 1/0 |DATA BUS (D1)13 P33 [e) VS-1 PS3 33 P52 1/0 | DATA BUS (D2)14 P70 oO RAM OD Signal Output 34 P53 0 DATA BUS (D3)15 P71 oO HD61602 €S Signal Output 35 P40 H/o DATA BUS (D4)16 P72 oO RAM and HD61602 R/W 36 PA1 1/0 DATA BUS (D5)17 P73 oO RAM CS7 Signal Output 37 P42 1/0 DATA BUS (D6)18 RESET Reset Input 38 P43 (70 | DATA BUS (D7)19 cli Clock 39 Vss GND20 VDD Power Supply 40 EVENT GNDTable 8 uPD7508H-056 Terminal functions (Control unit IC3)13