Lauterbach MMDSP Processor Architecture Manual

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Lauterbach MMDSP Processor Architecture Manual Manual pdf 14 page image

MMDSP Debugger 14©1989-2019 Lauterbach GmbHCPU specific SYStem CommandsSYStem.CONFIG Configure debugger according to target topologyThe four parameters IRPRE, IRPOST, DRPRE, DRPOST are required to inform the debugger about theTAP controller position in the JTAG chain, if there is more than one core in the JTAG chain (e.g. ARM +DSP). The information is required before the debugger can be activated e.g. by a SYStem.Up. See Daisy-chain Example.For some CPU selections (SYStem.CPU) the above setting might be automatically included, since therequired system configuration of these CPUs is known.TriState has to be used if several debuggers (“via separate cables”) are connected to a common JTAG portat the same time in order to ensure that always only one debugger drives the signal lines. TAPState andTCKLevel define the TAP state and TCK level which is selected when the debugger switches to tristatemode. Please note: nTRST must have a pull-up resistor on the target, TCK can have a pull-up or pull-downresistor, other trigger inputs need to be kept in inactive state.Format: SYStem.CONFIG SYStem.MultiCore (deprecated): CORE :(JTAG):DRPRE DRPOST IRPRE IRPOST TAPState TCKLevel TriState [ON | OFF]Slave [ON | OFF]Multicore debugging is not supported for the DEBUG INTERFACE (LA-7701).CORE For multicore debugging one TRACE32 GUI has to be started per core.To bundle several cores in one processor as required by the system thiscommand has to be used to define core and processor coordinates withinthe system topology.Further information can be found in SYStem.CONFIG.CORE.