NAD VISO FIVE Service Manual

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NAD VISO FIVE Service Manual Manual pdf 33 page image

PIN CONFIGURATIONV SSDQ15DQ14VSSQDQ13DQ12VDDQDQ11DQ10VSSQDQ9DQ8VDDQNCUDQMCLKCKENCA9A8A7A6A5A4VSS123456789101112131415161718192021222324255049484746454443424140393837363534333231302928V DDDQ0DQ1V SSQDQ2DQ3V DDQDQ4DQ5V SSQDQ6VDDQ/WE/CAS/RAS/CSA11A10A0A1A2A3V DD50pin TSOP II400mil x 825mil0.8mm pin pitch2726DQ7LDQMV SSDQ15DQ14VSSQDQ13DQ12VDDQDQ11DQ10VSSQDQ9DQ8VDDQNCUDQMCLKCKENCA9A8A7A6A5A4VSS123456789101112131415161718192021222324255049484746454443424140393837363534333231302928V DDDQ0DQ1V SSQDQ2DQ3V DDQDQ4DQ5V SSQDQ6VDDQ/WE/CAS/RAS/CSA11A10A0A1A2A3V DD50pin TSOP II400mil x 825mil0.8mm pin pitch2726DQ7LDQMPIN DESCRIPTIONPIN PIN NAME DESCRIPTIONCLK Clock The system clock input. All other inputs are referenced to the SDRAM on the risingedge of CLK.CKE Clock Enable Controls internal clock signal and when deactivated, the SDRAM will be one of thestates among power down, suspend or self refresh.CS Chip Select Command input enable or mask except CLK, CKE and DQMBA Bank Address Select either one of banks during both RAS and CAS activity.A0 ~ A10 Address Row Address : RA0 ~ RA10, Column Address : CA0 ~ CA7Auto-precharge flag : A10RAS, CAS, WERow Address Strobe,Column Address Strobe, WriteEnableRAS, CAS and WE define the operation.Refer function truth table for detailsLDQM, UDQM Data Input/Output Mask DQM control output buffer in read mode and mask input data in write modeDQ0 ~ DQ15 Data Input/Output Multiplexed data input / output pinV DD /V SS Power Supply/Ground Power supply for internal circuit and input bufferV DDQ/V SSQ Data Output Power/Ground Power supply for DQNC No Connection No connectionSD RAM : IC472-21