NAD VISO FIVE Service Manual

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NAD VISO FIVE Service Manual Manual pdf 35 page image

PIN ASSIGNMENTTop View123456789101112131415161718192021222324252627V DDDQ 0V DD QDQ 1DQ 2V S S QDQ 3DQ 4V DD QDQ 5DQ 6V S S QDQ 7V DDL DQ MW EC ASR ASCSA 13A 12A 10 /APA 0A 1A 2A 3V DD545352515049484746454443424140393837363534333231302928V SSDQ15V S S QDQ14DQ13V DD QDQ12DQ11V S S QDQ10DQ 9V DD QDQ 8V S SN CU D Q MCLKCKEN CA 11A 9A 8A 7A 6A 5A 4V S SFUNCTIONAL BLOCK DIAGRAMPIN FUNCTION DESCRIPTIONPIN NAME INPUT FUNCTIONCLK System Clock Active on the positive going edge to sample all inputsCS Chip Select Disables or enables device operation by masking or enabling allinputs except CLK , CKE and L(U)DQMCKE Clock EnableMasks system clock to freeze operation from the next clock cycle.CKE should be enabled at least one cycle prior new command.Disable input buffers for power down in standby.A0 ~ A11 Address Row / column address are multiplexed on the same pins.Row address : RA0~RA11, column address : CA0~CA7A12 , A13 Bank Select Address Selects bank to be activated during row address latch time.Selects bank for read / write during column address latch time.RAS Row Address StrobeLatches row addresses on the positive going edge of the CLK withRAS low.Enables row access & precharge.CAS Column Address StrobeLatches column address on the positive going edge of the CLK withCAS low.Enables column access.WE Write Enable Enables write operation and row precharge.Latches data in starting from CAS , WE active.L(U)DQM Data Input / Output Mask Makes data output Hi-Z, tSHZ after the clock and masks the output.Blocks data input when L(U)DQM active.DQ0 ~ DQ15 Data Input / Output Data inputs / outputs are multiplexed on the same pins.VDD / VSS Power Supply / Ground Power and ground for the input buffers and the core logic.VDDQ / VSSQ Data Output Power / Ground Isolated power supply and ground for the output buffers to provideimproved noise immunity.NC No Connection This pin is recommended to be left No Connection on the device.L(U)DQMDQModeRegistercigoLlortnoCColumnAddressBuffer&RefreshCounterRowAddressBuffer&RefreshCounterBank DredoceDwoRBank ABank BBank CSense AmplifierColumn DecoderData Control CircuittiucriChctaLtuptuO&tupnIreffuBAddressClockGeneratorCLKCKEredoceDdnammoCCSRASCASWE2-2364M SDRAM (M12L64164A) : IC12