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NEC 78K0S/KA1+ User Manual

Also see for 78K0S/KA1+: Application noteApplication noteApplication noteApplication notePreliminary user's manual

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Contents
  1. Table Of Contents
  2. Table Of Contents
  3. Table Of Contents
  4. Table Of Contents
  5. Table Of Contents
  6. Table Of Contents
  7. CHAPTER 1 OVERVIEW
  8. Ordering Information
  9. Pin Configuration (Top View)
  10. K0S/Kx1+ Product Lineup
  11. Block Diagram
  12. Functional Outline
  13. CHAPTER 2 PIN FUNCTIONS
  14. Pin Functions
  15. P40 to P45 (Port 4)
  16. AV REF
  17. CHAPTER 3 CPU ARCHITECTURE
  18. Internal program memory space
  19. Special function register (SFR) area
  20. Processor Registers
  21. General-purpose registers
  22. Special function registers (SFRs)
  23. Instruction Address Addressing
  24. Immediate addressing
  25. Register addressing
  26. Operand Address Addressing
  27. Short direct addressing
  28. Special function register (SFR) addressing
  30. Register indirect addressing
  31. Based addressing
  32. Stack addressing
  33. CHAPTER 4 PORT FUNCTIONS
  34. Port Configuration
  35. Port 2
  36. Port 3
  37. Port 4
  38. Port 12
  39. Port 13
  40. Operation of Port Function
  41. CHAPTER 5 CLOCK GENERATORS
  42. Configuration of Clock Generators
  43. Registers Controlling Clock Generators
  44. System Clock Oscillators
  45. External clock input circuit
  46. Operation of CPU Clock Generator
  47. Operation of Clock Generator Supplying Clock to Peripheral Hardware
  48. CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
  49. Configuration of 16-Bit Timer/Event Counter 00
  50. Registers to Control 16-Bit Timer/Event Counter 00
  51. Operation of 16-Bit Timer/Event Counter 00
  52. External event counter operation
  53. Pulse width measurement operations
  54. Square-wave output operation
  55. PPG output operations
  56. One-shot pulse output operation
  57. Cautions Related to 16-Bit Timer/Event Counter 00
  58. CHAPTER 7 8-BIT TIMER 80
  59. Configuration of 8-Bit Timer 80
  60. Register Controlling 8-Bit Timer 80
  61. Operation of 8-Bit Timer 80
  62. Notes on 8-Bit Timer 80
  63. CHAPTER 8 8-BIT TIMER H1
  64. Registers Controlling 8-Bit Timer H1
  65. Operation of 8-Bit Timer H1
  66. Operation as PWM output mode
  67. CHAPTER 9 WATCHDOG TIMER
  68. Configuration of Watchdog Timer
  69. Registers Controlling Watchdog Timer
  70. Operation of Watchdog Timer
  71. Watchdog timer operation when "low-speed internal oscillator can be stopped by software" is selected by option byte
  72. Watchdog timer operation in STOP mode (when "low-speed internal oscillator can be stopped by software" is selected by option byte)
  73. Watchdog timer operation in HALT mode (when "low-speed internal oscillator can be stopped by software" is selected by option byte)
  74. CHAPTER 10 A/D CONVERTER
  75. Configuration of A/D Converter
  76. Registers Used by A/D Converter
  77. A/D Converter Operations
  78. Input voltage and conversion results
  79. A/D converter operation mode
  80. How to Read A/D Converter Characteristics Table
  81. Cautions for A/D Converter
  82. CHAPTER 11 SERIAL INTERFACE UART6
  83. Configuration of Serial Interface UART6
  84. Registers Controlling Serial Interface UART6
  85. Operation of Serial Interface UART6
  86. Asynchronous serial interface (UART) mode
  87. Dedicated baud rate generator
  88. CHAPTER 12 INTERRUPT FUNCTIONS
  89. Interrupt Function Control Registers
  90. Interrupt Servicing Operation
  91. Multiple interrupt servicing
  92. Interrupt request pending
  93. CHAPTER 13 STANDBY FUNCTION
  94. Registers used during standby
  95. Standby Function Operation
  96. STOP mode
  97. CHAPTER 14 RESET FUNCTION
  98. Register for Confirming Reset Source
  99. CHAPTER 15 POWER-ON-CLEAR CIRCUIT
  100. Configuration of Power-on-Clear Circuit
  101. Cautions for Power-on-Clear Circuit
  102. CHAPTER 16 LOW-VOLTAGE DETECTOR
  103. Registers Controlling Low-Voltage Detector
  104. Operation of Low-Voltage Detector
  105. Cautions for Low-Voltage Detector
  106. CHAPTER 17 OPTION BYTE
  107. Format of Option Byte
  108. CHAPTER 18 FLASH MEMORY
  109. Memory Configuration
  111. Writing with Flash Programmer
  112. Programming Environment
  113. Pin Connection on Board
  114. RESET pin
  115. Port pins
  116. On-Board and Off-Board Flash Memory Programming
  117. Security settings
  118. Flash Memory Programming by Self Writing
  119. Cautions on self programming function
  120. Example of shifting normal mode to self programming mode
  121. Example of shifting self programming mode to normal mode
  122. Example of block erase operation in self programming mode
  123. Example of block blank check operation in self programming mode
  124. Example of byte write operation in self programming mode
  125. Example of internal verify operation in self programming mode
  126. Examples of operation when command execution time should be minimized in self programming mode
  127. Examples of operation when interrupt-disabled time should be minimized in self programming mode
  128. CHAPTER 19 INSTRUCTION SET OVERVIEW
  129. Description of "Operation" column
  130. Operation List
  131. Instructions Listed by Addressing Type
  132. CHAPTER 20 ELECTRICAL SPECIFICATIONS ((T) product, (S) product, (R) product, (A) product
  144. CHAPTER 21 ELECTRICAL SPECIFICATIONS (TARGET VALUES) ((T2) product)
  145. CHAPTER 22 ELECTRICAL SPECIFICATIONS (TARGET VALUES) ((A2) product)
  146. CHAPTER 23 PACKAGE DRAWING
  147. CHAPTER 24 PACKAGE MARKING INFORMATION
  148. CHAPTER 25 RECOMMENDED SOLDERING CONDITIONS
  149. APPENDIX A DEVELOPMENT TOOLS
  150. A.1 Software Package
  151. A.3 Control Software
  152. A.5 Debugging Tools (Hardware)
  153. A.6 Debugging Tools (Software)
  154. APPENDIX B NOTES ON TARGET SYSTEM DESIGN
  155. APPENDIX C REGISTER INDEX
  156. C.2 Register Index (Symbol)
  157. APPENDIX D LIST OF CAUTIONS
  158. E.1 Major Revisions in This Edition
  159. E.2 Revision History up to Previous Editions
NEC 78K0S/KA1+ User Manual Manual pdf 1 page image
User’s ManualμPD78F9221μPD78F922278K0S/KA1+8-Bit Single-Chip Microcontrollers©Printed in JapanDocument No. U16898EJ3V0UD00 (3rd edition)Date Published July 2005 NS CP(K)2003
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78K0S/KA1+
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