78CHAPTER 5 CLOCK GENERATOR5.6.2 CPU clock switching procedureThis section describes CPU clock switching procedure.Figure 5-7. CPU Clock Switching(1) The CPU is reset by setting the RESET signal to low level after power-on. After that, when reset is releasedby setting the RESET signal to high level, main system clock starts oscillation. At this time, oscillationstabilization time (2 17/f X) is secured automatically.After that, the CPU starts executing the instruction at the minimum speed of the main system clock (12.8μs whenoperated at 5.0 MHz).(2) After the lapse of a sufficient time for the V DD voltage to increase to enable operation at maximum speeds,the processor clock control register (PCC) and oscillation mode selection register (OSMS) are rewritten andthe maximum-speed operation is carried out.VDDRESETCPU ClockWait (26.2 ms : 5.0 MHz)Internal Reset OperationMinimumSpeedOperationMaximum SpeedOperation
