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NEC PD78081(A) User Manual

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Contents
  1. Table Of Contents
  2. Table Of Contents
  3. Table Of Contents
  4. Table Of Contents
  5. Table Of Contents
  6. Table Of Contents
  7. Table Of Contents
  8. Table Of Contents
  9. CHAPTER 1 OUTLINE
  10. Applications
  11. Quality Grade
  12. Pin Configuration (Top View)
  13. K/0 Series Development
  14. Block Diagram
  15. Outline of Function
  16. CHAPTER 2 PIN FUNCTION
  17. PROM programming mode pins ( PD78P083 only)
  18. Description of Pin Functions
  19. P30 to P37 (Port 3)
  20. P70 to P72 (Port 7)
  21. AV REF
  22. IC (Mask ROM version only)
  23. Pin Input/Output Circuits and Recommended Connection of Unused Pins
  24. Pin Input/Output Circuit of List
  25. CHAPTER 3 CPU ARCHITECTURE
  26. Memory Map ( PD78082)
  27. Memory Map ( PD78P083)
  28. Internal program memory space
  29. Internal data memory space
  30. Data Memory Addressing ( PD78081)
  31. Data Memory Addressing ( PD78082)
  32. Data Memory Addressing ( PD78P083)
  33. Processor Registers
  34. Stack Pointer Configuration
  35. General registers
  36. Special Function Register (SFR)
  37. Instruction Address Addressing
  38. Immediate addressing
  39. Table indirect addressing
  40. Register addressing
  41. Operand Address Addressing
  43. Direct addressing
  44. Short direct addressing
  45. Special-Function Register (SFR) addressing
  46. Register indirect addressing
  47. Based addressing
  48. Based indexed addressing
  49. CHAPTER 4 PORT FUNCTIONS
  50. Port Configuration
  51. P00 Block Diagram
  52. Port 1
  53. Port 3
  54. Port 5
  55. Port 7
  56. P71 and P72 Block Diagram
  57. Port 10
  58. Port Function Control Registers
  59. Port Mode Register Format
  60. Pull-Up Resistor Option Register Format
  61. Port Function Operations
  62. CHAPTER 5 CLOCK GENERATOR
  63. Block Diagram of Clock Generator
  64. Clock Generator Control Register
  65. Oscillation Mode Selection Register Format
  66. System Clock Oscillator
  67. Examples of Oscillator with Bad Connection (1/2)
  68. Scaler
  69. Clock Generator Operations
  70. Changing CPU Clock Settings
  71. CPU clock switching procedure
  72. CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6
  73. Bit Timer/Event Counters 5 and 6 Functions
  74. Bit Timer/Event Counters 5 and 6 Configurations
  75. Block Diagram of 8-Bit Timer/Event Counters 5 and 6 Output Control Circuit
  76. Bit Timer/Event Counters 5 and 6 Control Registers
  77. Timer Clock Select Register 5 Format
  78. Timer Clock Select Register 6 Format
  79. Bit Timer Mode Control Register 5 Format
  80. Bit Timer Mode Control Register 6 Format
  81. Port Mode Register 10 Format
  82. Bit Timer/Event Counters 5 and 6 Operations
  83. Interval Timer Operation Timings
  84. External event counter operation
  85. Square-wave output
  86. PWM output operations
  87. PWM Output Operation Timing (Active high setting)
  88. PWM Output Operation Timings (CRn0 = FFH, active high setting)
  89. Cautions on 8-Bit Timer/Event Counters 5 and 6
  90. Timing after Compare Register Change during Timer Count Operation
  91. CHAPTER 7 WATCHDOG TIMER
  92. Watchdog Timer Configuration
  93. Watchdog Timer Control Registers
  94. Timer Clock Select Register 2 Format
  95. Watchdog Timer Mode Register Format
  96. Watchdog Timer Operations
  97. Interval timer operation
  98. CHAPTER 8 CLOCK OUTPUT CONTROL CIRCUIT
  99. Clock Output Control Circuit Configuration
  100. Clock Output Function Control Registers
  101. Port Mode Register 3 Format
  102. CHAPTER 9 BUZZER OUTPUT CONTROL CIRCUIT
  103. Buzzer Output Function Control Registers
  106. CHAPTER 10 A/D CONVERTER
  107. A/D Converter Block Diagram
  108. A/D Converter Control Registers
  109. A/D Converter Mode Register Format
  110. A/D Converter Input Select Register Format
  111. External Interrupt Mode Register 1 Format
  112. A/D Converter Operations
  113. A/D Converter Basic Operation
  114. Input voltage and conversion results
  115. A/D converter operating mode
  116. A/D Conversion by Software Start
  117. A/D Converter Cautions
  118. Analog Input Pin Disposition
  119. CHAPTER 11 SERIAL INTERFACE CHANNEL 2
  120. Serial Interface Channel 2 Configuration
  121. Serial Interface Channel 2 Block Diagram
  122. Baud Rate Generator Block Diagram
  123. Serial Interface Channel 2 Control Registers
  124. Asynchronous Serial Interface Mode Register Format
  125. Asynchronous Serial Interface Status Register Format
  126. Baud Rate Generator Control Register Format (1/2)
  127. Baud Rate Generator Control Register Format (2/2)
  128. Serial Interface Channel 2 Operation
  129. Asynchronous serial interface (UART) mode
  130. Asynchronous Serial Interface Transmit/Receive Data Format
  131. Asynchronous Serial Interface Transmission Completion Interrupt Request Timing
  132. Asynchronous Serial Interface Reception Completion Interrupt Request Timing
  133. Receive Error Timing
  134. wire serial I/O mode
  135. Wire serial I/O Mode Timing
  136. Circuit of Switching in Transfer Bit Order
  137. CHAPTER 12 INTERRUPT FUNCTION
  138. Interrupt Sources and Configuration
  139. Basic Configuration of Interrupt Function (1/2)
  140. Basic Configuration of Interrupt Function (2/2)
  141. Interrupt Function Control Registers
  142. Interrupt Request Flag Register Format
  143. Interrupt Mask Flag Register Format
  144. Priority Specify Flag Register Format
  145. External Interrupt Mode Register 0 Format
  146. Program Status Word Configuration
  147. Interrupt Servicing Operations
  148. Flowchart from Non-Maskable Interrupt Request Generation to Acknowledgment
  149. Non-Maskable Interrupt Request Acknowledge Operation
  150. Maskable interrupt request acknowledge operation
  151. Interrupt Request Acknowledge Processing Algorithm
  152. Interrupt Request Acknowledge Timing (Minimum Time)
  153. Software interrupt request acknowledge operation
  154. Interrupt request reserve
  155. Interrupt Request Hold
  156. CHAPTER 13 STANDBY FUNCTION
  157. Standby function control register
  158. Standby Function Operations
  159. HALT Mode Clear upon Interrupt Generation
  160. HALT Mode Release by RESET Input
  161. STOP mode
  162. STOP Mode Release by Interrupt Generation
  163. Release by STOP Mode RESET Input
  164. CHAPTER 14 RESET FUNCTION
  165. Timing of Reset Input by RESET Input
  166. CHAPTER 15 PD78P083
  167. Memory Size Switching Register
  168. PROM Programming
  169. PROM write procedure
  170. Page Program Mode Timing
  171. Byte Program Mode Flowchart
  172. Byte Program Mode Timing
  173. PROM reading procedure
  174. Erasure Procedure ( PD78P083DU Only)
  175. CHAPTER 16 INSTRUCTION SET
  176. Legends Used in Operation List
  177. Description of "operation" column
  178. Operation List
  179. Instructions Listed by Addressing Type
  180. APPENDIX A DEVELOPMENT TOOLS
  181. A.1 Language Processing Software
  182. A.2 PROM Programming Tools
  183. A.3 Debugging Tools
  184. A.3.2 Software (1/3)
  185. A.3.2 Software (2/3)
  186. A.3.2 Software (3/3)
  187. In-Circuit Emulator
  188. APPENDIX B EMBEDDED SOFTWARE
  189. B.1 Real-time OS
  190. B.2 Fuzzy Inference Development Support System
  191. APPENDIX C REGISTER INDEX
  192. APPENDIX D REVISION HISTORY
NEC PD78081(A) User Manual Manual pdf 53 page image
30CHAPTER 3 CPU ARCHITECTUREFigure 3-4. Data Memory Addressing (μPD78081)General Registers32 × 8 bitsInternal ROM8192 × 8 bitsUnusableInternal High-speed RAM256 × 8 bitsSpecial FunctionRegisters (SFRs)256 × 8 bits SFR AddressingRegister Addressing Short DirectAddressingDirect AddressingRegister IndirectAddressingBased AddressingBased IndexedAddressingF F 2 0 HFF1FHF F 0 0 HFEFFHFEE0HFEDFHFE20HFE1FHFE00HFDFFH2 0 0 0 H1FFFHFFFFH0 0 0 0 H
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This manual is suitable for:
NEC PD78081NEC PD78081(A)NEC PD78082NEC PD78082(A)NEC PD78083NEC PD78P081(A2)NEC PD78P083NEC PD78P083(A)uPD78081uPD78081(A)uPD78082uPD78082(A)uPD78083 SUBSERIESuPD78P081(A2)uPD78P083uPD78P083(A)
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