NXP Semiconductors Digital DNA MSC8102 User Manual And Hardware Detailed Design Description

NXP Semiconductors Digital DNA MSC8102 User Manual And Hardware Detailed Design Description Manual pdf 18 page image

13 PFC_DDD_v1.3.docFigure 6. PFC to DSI Interface5.2.3.2 MSC8101 60x to DSI Interface: Asynchronous modeThe DSI can be asynchronously controlled via the following UPM signals:Table 14. DSI Asynchronous signalsUPM Signal DescriptionCS3 Broadcast Chip SelectCS4 Chip SelectPBS[0:7] Byte StrobePGPL2 General PurposePGPL4/UPMWAIT UPMWAITThese signals are routed through the FPGA, which operates in transparent mode.5.2.4 MSC8101 to MSC8102 Interrupt ConnectivityThe FPGA is used to route the interrupts/GPIO lines between the MSC8101 and MSC8102s. Forflexibility the MSC8101 has 5 GPIO lines (PC4, PC5, PC24, PC25 & PC30) connected to the FPGAand in turn receives 7 IRQ inputs from the FPGA. Each MSC8102 has GPIO30 and INT_OUTconnected to the FPGA, with their respective IRQ1 and IRQ2 also connected, Figure 7. The standardpre-programmed FPGA interrupt routing is shown in Figure 8.Dh[0:63]A_TSIZ[0:3]Xilinix XC2S300E -7F-G456CMSC8101A_PSDQM[0:7]FPGA_CKA_TSA_TBSTA_PSDVALA_CLK_OUTAh[0:31]A_TT[0:4]A_BADDR[27:31]A_BCTL[0:1]GRP_Ah[7:29]A_AACKA_TAA_CS_HCSA_CS_HBCSA_ALEGRP_Ds[0:63]HBRSTHBCSHCSHTAHRWHWBS[0:7]HD[0:63]GRP_Ah[11:29] HA[11:29]GRP_Ah[7:10] HCID[0:3]CHIP_ID[0:3]MSC8102 – CHIP_ID[0:3]--------------------------DSP1 0000DSP2 0001DSP3 0010DSP4 0011DSP5 0100HDST[0:1]3V3HCK_D[1:5]HCLKINHCK_D1HCK_D2HCK_D3HCK_D4HCK_D5MSC8102[x5]FPGICS9112(Zero delay buffer)PGPL2A_PUPMWAITNote: All unused PPCsignals on host side pulledhighDh[0:63]A_TSIZ[0:3]Xilinix XC2S300E -7F-G456CMSC8101A_PSDQM[0:7]FPGA_CKA_TSA_TBSTA_PSDVALA_CLK_OUTAh[0:31]A_TT[0:4]A_BADDR[27:31]A_BCTL[0:1]GRP_Ah[7:29]A_AACKA_TAA_CS_HCSA_CS_HBCSA_ALEGRP_Ds[0:63]HBRSTHBCSHCSHTAHRWHWBS[0:7]HD[0:63]GRP_Ah[11:29] HA[11:29]GRP_Ah[7:10] HCID[0:3]CHIP_ID[0:3]MSC8102 – CHIP_ID[0:3]--------------------------DSP1 0000DSP2 0001DSP3 0010DSP4 0011DSP5 0100HDST[0:1]3V3HCK_D[1:5]HCLKINHCK_D1HCK_D2HCK_D3HCK_D4HCK_D5MSC8102[x5]FPGAICS9112(Zero delay buffer)PGPL2A_PUPMWAITNote: All unused PPCsignals on host side pulledhigh