NXP Semiconductors Digital DNA MSC8102 User Manual And Hardware Detailed Design Description

NXP Semiconductors Digital DNA MSC8102 User Manual And Hardware Detailed Design Description Manual pdf 26 page image

21 PFC_DDD_v1.3.docTDM2 TDM2TDATTDM2RDATCT_D12CT_D13TDM3 TDM3TDATTDM3RDATCT_D18CT_D19MSC8102 #4 TDM0 TDM0TDATTDM0RDATCT_D14CT_D15TDM1 TDM1TDATTDM1RDATCT_D10CT_D11TDM2 TDM2TDATTDM2RDATCT_D16CT_D17TDM3 TDM3TDATTDM3RDATCT_D8CT_D9MSC8102 #5 TDM0 TDM0TDATTDM0RDATCT_D14CT_D15TDM1 TDM1TDATTDM1RDATCT_D10CT_D11TDM2 TDM2TDATTDM2RDATCT_D16CT_D17TDM3 TDM3TDATTDM3RDATCT_D8CT_D9Table 20. TDM to CT Stream RoutingThe MSC8102s are configured in their four-pin setup with common clock and frame syncs for receiveand transmit. The clock and Frame Sync signals routed from the PTMC CT Bus are CT_8_A andCT_FRAME_A respectively.5.3.4 MSC8102 RS232 InterfaceA simple RS232 UART is provided through the MSC8102’s serial communications interface (SCI) togive programmable debug or communications capability. A Maxim MAX3232CUE provides the levelconversion for the interface. Note that the receiver inputs are pulled low internally while thetransmitter inputs have external pull-ups.5.4 General Board Configuration5.4.1 ResetFigure 12 illustrates the reset scheme. The MAXIM MAX6828 generates the primary reset for the PFC(PORESET), which is supplied to the MSC8101, MSC8102s (AND with MSC8101 GPIO: PA7),FPGA and Flash memory. The Open drain output (RESET_N) is pulled low (for a minimum time outperiod of 140ms) when any of the following conditions occur:• MR_N is pulled low via the pushbutton switch SW1• The 1V6 voltage monitor trip voltage is reached (1.23Von Reset In pin),)121210(63.0_ RRRtripVmonitor +=• The threshold voltage on 3V3 is reached (MIN = 2.85V, MAX = 3.00V, TYP = 2.93V)