NXP Semiconductors MIMXRT1050 Hardware User's Manual

Also see for MIMXRT1050: Hardware user's guide Development guide

Contents

SpecificationsMIMXRT1050 EVK Board Hardware User’s Guide, User's Guide, Rev. 2, 03/2018NXP Semiconductors 9Figure 5. Power Control DiagramNOTEPower Control Diagram described in MIMXRT1050 EVK Board is true for A0 silicon For A1silicon, DCDC_IN is expected to be powered with other domains together.In the other word, for A0 silicon the DCDC_IN is powered with LDO (Path 1). And for A1 silicon, itis expected to be powered with DC/DC (Path 2).For A0 silicon, please following above power logic as if not power the SNVS together withDCDC_IN, the on chip DCDC module will not power up correctly.The power rails on the board are shown in Table 5.Table 5. Power RailsPower Rail MIN(V)TYP(V)MAX(V) DescriptionVDD_SOC_IN 0.925 -- 1.26 Core supplies input voltageVDD_HIGH_IN 3 3.3 3.6 VDD_HIGH_IN supply voltageDCDC_IN 3¹ 3.3¹ 3.6¹ Power for DCDC