TWR-KL28Z Hardware DescriptionTWR-KL28Z User’s Guide, Rev. 0, 06/20166 NXP SemiconductorsMCU, cut the jumper between pin1 and pin2 of J32/J33 on bottom layer. This will disconnect theSWD_CLK pin to the KL28Z so that it will interfere with the communications to an off-board MCUconnected to J30. Figure 5 shows SWD connector signals description for KL28Z.Figure 5. SWD debug connector to KL28Z4.2.2. Virtual serial portA serial port connection is available between the CMSIS-DAP MCU and pins PTA1 and PTA2 of theKL28Z. Several of the default CMSIS-DAP applications are provided by NXP, including the MSDFlash Programmer and the CMSIS-DAP USB HID interface, providing a USB communications deviceclass (CDC) interface that bridges serial communications between the USB host and this serial interface.4.3. MicrocontrollerThe TWR-KL28Z is a MCU module featuring the MKL28Z512VLL7, a Kinetis microcontroller withUSB 2.0 full-speed OTG controller in a 100 LQFP package. An on-board debug circuit, CMSIS-DAP,provides a SWD interface and a power supply input through a mini-USB connector, as well as serial toUSB and CDC class compliant UART interface.Table 3. Features of MKL28Z512VLL7Feature DescriptionUltra-low-power- 10 low-power modes with power and clock gating for optimal peripheral activity andrecovery times. Stop currents of <190 nA (VLLS0), run currents of <280 uA/MHz, 4 s wake-up from Stop mode- Full memory and analog operation down to 1.71 V for extended battery life- Low-leakage wake-up unit with up to eight internal modules and eight pins as wake-upsources in low-leakage stop (LLS)/very low-leakage stop (VLLS) modes- Low-power timer for continual system operation in reduced power statesFlash, SRAM, ROM- 512 KB flash featuring fast access times, high reliability, and four levels of securityprotection. No user or system intervention to complete programming and erase functionsand full operation down to 1.71 V- 128 KB of SRAM- 32 KB of ROM with Kinetis bootloader included (UART, SPI, I2C, USB-HID)