Chapter 4 Signal Connections©National Instruments Corporation4-45PCI E Series User ManualGPCTR1_UP_DOWN SignalThis signal can be externally input on the DIO7 pin and is not availableas an output on the I/O connector. General-purpose counter 1 countsdown when this pin is at a logic low and counts up at a logic high.This input can be disabled so that software can control the up-downfunctionality and leave the DIO7 pin free for general use. Figure 4-36shows the timing requirements for the GATE and SOURCE inputsignals and the timing specifications for the OUT output signals of yourPCI E Series board.Figure 4-36. GPCTR Timing SummaryThe GATE and OUT signal transitions shown in Figure 4-36 arereferenced to the rising edge of the SOURCE signal. This timingdiagram assumes that the counters are programmed to count risingedges. The same timing diagram, but with the source signal invertedand referenced to the falling edge of the source signal, would applywhen the counter is programmed to count falling edges.The GATE input timing parameters are referenced to the signal at theSOURCE input or to one of the internally generated signals on yourPCI E Series board. Figure 4-36 shows the GATE signal referenced tothe rising edge of a source signal. The gate must be valid (either high orSOURCE V IHV ILV IHV ILt sc t spt gsu t ght gwGATEt outOUT V OHV OLsctttttt 50 ns minimumsp 23 ns minimumgsu 10 ns minimumgh 0 ns minimumgw 10 ns minimumout 80 ns maximumSource Clock PeriodSource Pulse WidthGate Setup TimeGate Hold TimeGate Pulse WidthOutput Delay Timet sp
