Neoway N21 Series Hardware User's Manual

Neoway N21 Series Hardware User's Manual Manual pdf 18 page image

N21Hardware User GuideCopyright © Neoway Technology Co., Ltd. All rights reserved. 9Figure 3-2 Recommended schematic design 2SGDR4100 kΩC410 μFQ2Q1TVS2 C3470 μFC50.1 μFC6100pFC733 pFR12 kΩR210 kΩC110 μFC20.1 μFBCEVIN (3.6V) VBATPWR_ENSchematic Design Guidelines Select an enhanced p-MOSFET at Q1, of which the maximum safe operating voltage and draincurrent is high and Rds is low. Select a common NPN bipolar transistor or a digital NPN bipolar transistor at Q2. Reserveenough tolerances of resistors at R1 and R2 in design, especially for the situation in whichoperating voltage of the bipolar transistor might increase in low temperature. Place TVS2 close to the input interface of the power supply to clamp the surge voltage before itenters back-end circuits. Therefore, the back-end components and the module are protected. Place C3 close to the module. A large bypass tantalum capacitor (220 μF or 100 μF) or aluminumcapacitor (470 μF or 1000 μF) is expected at C1 to reduce voltage drops during bursts. Itsmaximum safe operating voltage should be higher than 1.5 times the voltage across the powersupply. Place a low-ESR bypass capacitor close to the module to filter out high-frequency noise from thepower supply.PCB Layout GuidelinesPlace an ESR capacitor at the output of the power supply to absorb surge current. Place a TVS diodeat the input of VBAT to protect back-end components. The layout of components and PCB trace arecritical to the hardware design of a device. Follow rules below in the power supply design: TVS diodes dissipate the transient pulse power during a surge and can handle a peak pulsecurrent of dozens or more than 100 A. They have a short response time. Place the TVS as closeto the interface as possible to ensure that the surge voltage can be clamped before the pulse iscoupled to the neighbor traces.