Nintendo GAME BOY Programming Manual

Also see for Game Boy Link Cable: Supplementary guide Manual User guide Instruction booklet User guide

Nintendo GAME BOY Programming Manual Manual pdf 22 page image

Game Boy Programming Manual222.3 Description of CPU FunctionsInterruptsThere are five types of interrupts available, including 4 types of maskable internal interruptsand 1 type of maskable external interrupt. The IE flag is used to control interrupts. The IFflag indicates which type of interrupt is set.! LCD Display Vertical Blanking! Status Interrupts from LCDC (4 modes)! Timer Overflow Interrupt! Serial Transfer Completion Interrupt! End of Input Signal for ports P10-P13DMA TransfersDMA transfers are controlled by the DMA registers.DMG allows 40 x 32-bit DMA transfers from 8000h-DFFFh to OAM (FE00h-FE9Fh).The transfer start address can be specified in increments of 100h for 8000h-DFFFh.In addition to the DMA transfers method for DMG (from 0000h-DFFFh in CGB), CGBenables two new types of DMA transfer — horizontal blanking and general-purpose DMAtransfers.Note, however, that when performing a DMG-type DMA transfer on CGB, someconsideration must be given to specifying the destination RAM area.For more information, see the DMA Functions section in Chapter 2.1 Horizontal Blanking DMA TransferSixteen bytes of data are automatically transferred for each horizontal blanking periodduring a DMA transfer from the user program area (0000h-7FFFh) or external andhardware working RAM area (A000h-DFFFh) to the LCD display RAM area(8000h-9FFFh).2 General-Purpose DMA TransferBetween 16 and 2048 bytes of data (specified in 16-byte increments) are transferredfrom the user program area (0000h-7FFFh) or external and hardware working RAMarea (A000h-DFFFh) to the LCD display RAM area (8000h-9FFFh), during theVertical Blanking Period.TimerThe timer is composed of the following:! TIMA (timer counter)! TMA (timer modulo register)! TAC (timer control register)Controller Connections! P10-P13: Input ports! P14-P15: The key matrix structure is composed of the output ports.At user program startup, the status of the CPU port registers and mode registers are asfollows.