Nokia NSE–3 SERIES Service Manual

Contents

Nokia NSE–3 SERIES Service Manual Manual pdf 50 page image

PAMSTechnical DocumentationNSE–3System ModuleOriginal 11/97Page 3 – 44MCU Memory MapMAD2 supports maximum of 4GB internal and 4MB external addressspace. External memories use address lines MCUAd0 to MCUAd21 and16–bit databus. The BUSC bus controller supports 8– and 16–bit accessfor byte, double byte, word and double word data. Access wait state 2and used databus width can be selected separately for each memoryblock.Flash ProgrammingThe phone have to be connected to the flash loading adapter FLA–5 sothat supply voltage for the phone and data transmission lines can be sup-plied from/to FLA–5. When FLA–5 switches supply voltage to the phone,the program execution starts from the BOOT ROM and the MCU investi-gates in the early start–up sequence if the flash prommer is connected.This is done by checking the status of the MBUS–line. Normally this lineis high but when the flash prommer is connected the line is forced low bythe prommer.The flash prommer serial data receive line is in receive mode waiting foran acknowledgement from the phone. The data transmit line from thebaseband to the prommer is initially high. When the baseband has recog-nized the flash prommer, the TX–line is pulled low. This acknowledge-ment is used to start to toggle MBUS (FCLK) line three times in order thatMAD2 gets initialized. This must be happened within 15 ms after TX lineis pulled low. After that the data transfer of the first two bytes from theflash prommer to the baseband on the RX–line must be done within 1 ms.When MAD2 has received the secondary boot byte count information, itforces TX line high. Now, the secondary boot code must be sent to thephone within 10 ms per 16 bit word. If these timeout values are exceeded,the MCU (MAD2) starts normal code execution from flash. After this, thetiming between the phone and the flash prommer is handled with dummybites.A 5V programming voltage is supplied inside the transceiver from the bat-tery voltage with a switch mode regulator (5V/30mA) of the CCONT. The5V is connected to VPP pin of the flash through the UI board.COBBA–GJThe COBBA–GJ provides an interface between the baseband and theRF–circuitry. COBBA–GJ performs analogue to digital conversion of thereceive signal. For transmit path COBBA_GJ performs digital to analogueconversion of the transmit amplifier power control ramp and the in–phaseand quadrature signals. A slow speed digital to analogue converter willprovide automatic frequency control (AFC).The COBBA asic is at any time connected to MAD asic with two inter-faces, one for transferring tx and rx data between MAD and COBBA andone for transferring codec rx/tx samples.