Panasonic EB-GD90 Technical Manual

Also see for EB-GD90: Operating instructions

Contents

http://cxema.ruGEMINIIssue A Section 7 MCUK981201G8Revision 0 – 32 – Technical Guide7.2.3 Memory InterfaceThe memory interface allows the 32 bit CPU to access 16 and 8 bit devices, and allows the addition of wait states to memoryaccess. The memory interface allows between 0 and 7 wait states to be added. The ROM area is hardware write protected, aFLASH write enable bit in the ROM wait state configuration register can be used to enable write access the ROM area.7.2.4 Interrupt HandlerThe ARM CPU has two interrupts, FIQ is a Fast non-maskable interrupt and IRQ is a standard maskable interrupt.Gemini has 11 interrupt sources. The Interrupt handler assigns priorities to these interrupts and routes them to either the FIQor IRQ inputs of the ARM CPU. Additionally, the interrupt handler controls waking up of the CPU on receiving an unmaskedinterrupt, if the CPU is in sleep mode.For GD90 the FIQ interrupt is reserved for the power supply fail priority interrupt.CPU Memory MAPDevice Name Start address Size Use Bus widthROM 0000:0000 2M FLASH 2 Mbytes 16 bitsRAM 0020:0000 2M RAM 256 kbytes 8 bitsBUS CNTRL 0040:0000 1M wait state registers 16 bitsAPI RAM 0050:0000 8k CPU/DSP shared ram 16 bitsAPIC 0050:4000 1k CPU/DSP interface controller 16 bitsTPU RAM 0050:4400 1k GSM timer Microcode RAM 16 bitsSIM 0050:4800 1k SIM interface 16 bitsTSP 0050:4C00 1k Timed Serial port 16 bitsINTH 0050:5000 1k Interrupt controller 16 bitsTPU REG 0050:5400 1k GSM timer registers 16 bitsCLKM 0050:5800 1k Clock control module 16 bitsTIMER 0050:5C00 1k software timers 16 bitsAPIF 0050:6000 1k ARM peripheral interface 16 bitsUWIRE 0050:6400 1k Synchronous Serial port 16 bitsARMIO 0050:6800 1k Keypad, buzzer, LCD & I/O 16 bits8251 0050:6C00 1k UART 16 bitsCS2 0060:0000 2M LCD driver 8 bitsnCS0 0080:0000 2M Extended I/O 8 bitsnCS1 00A0:0000 2M not used -Interrupt Level AssignmentsInterrupt source Description Interrupt detectionIRQ_TIM1 Buzzer timer Edge sensitiveIRQ_TIM2 operating system timer Edge sensitiveIRQ_API DSP Interface interrupt Rising Edge sensitiveIRQ_EXT Power supply fail interrupt Low Level sensitiveIRQ_USART UART Interrupt Level sensitiveIRQ_ARMIO Keypad Interrupt Low for 1 clock periodIRQ_FRAME Frame Interrupt Edge sensitiveIRQ_PAGE Page Interrupt Edge sensitiveIRQ_TIM_GSM Edge sensitiveIRQ_TSP Timed serial port Interrupt Edge sensitiveIRQ_SIM SIM Interrupt Level sensitiveIRQ_F_USART Fast interrupt from USART Level sensitiveIRQ_RSS Radio subsystem interrupt Edge sensitive