RCA CDP18S711 Instruction Manual
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Contents
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21V. Logic DescriptionA complete set of logic diagrams is provided inAppendix E. Power requirements for a system with 2048bytes of RAM is 5 V DC at 350 mA. If you wish toexpand the system you can use your own higher currentpower supply.This system is designed around the CDP1802microprocessor Wfl. Refer to the CDP1802 data sheetand User Manual for the CDPI802 COSMACMicroprocessor MPM-201A for a complete descriptionof its operation. The CDP1802 requires a square-waveclock input at pin 1 for operation. This system uses a1.7609-MHz clock. One half of U3 is connected as afree-running crystal-controlled oscillator. A3.52180-MHz crystal is used in this circuit. The output ofthis 3.52180-MHz oscillator is then divided by 2 usingU4 to provide the 1.7609MHz input clock for theCDP1802. Because each CDP1802 machine cycle equals8 clock cycles, each machine cycle is about 4.54 us induration. TPA and TPB are timing pulses generated onceeach machine cycle by the CDP 1802 microprocessor.How Memory Is AddressedA debounced RUN level goes high when the RUNswitch is flipped up. This signal causes the CDP1802 tobegin fetching instructions from memory. When theRUN switch is down, the CDP1802 is held in a resetstate and U6A (in Fig. E-2) is reset. U6B is held set byU6A. The CDP1802 starts fetching instructions from theROM (U10) at location 8000 since UOB is being heldset. The ROM contains theoperating system program which uses a 64 instruction togenerate an N2 pulse. This-N2 pulse sets U6A so it nolonger holds U6B in its set state. From this point on, theselection,of RAM or ROM locations is controlled by themost significant address bit latched into U6B each cycleby TPA.U8 latches an additional 4 address bits to provide the1-9-bit address required in a 4096-byte RAM system.U9A decodes 2 of these address bits into 4 lines whichare used to select up to four 1024-byte RAM sections.Each 1024-byte section of RAM consists of two 4 x1024-bit RAM IC's (U16-U23 in Fig. E-4). Only the firsttwo sections of RAM (U16-U19) are used in a 2048-bytesystem. U9B in Fig. E-2 is wired as a simple gate thatinhibits selecting any section of RAM when either theROM is selected or a positive RAM inhibit signal isgenerated on pin 19 of the expansion interface byexternal circuits.Memory read (MRD) and write (MWR) signals aresupplied to the RAM at appropriate times by theCDP1802. Data is transferred between memory,CDP1802, input, or output via an 8-bit data bus. Pull-upresistors are provided on this bus for compatibility withTTL signal swings provided by some RAMs.How the Input/Output WorksUll and U12 in Fig. E-3 are used to decode theinput/output instruction codes used in the system.U13 provides the hex keyboard interface. Thisinterface permits a program to determine which key is |
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