Contents - Alphabetical Listing of Instructions
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Document Conventions
- Processor Registers
- OpCode Descriptions
- ADC HL,ss
- ADD HL,ss
- ADD IX,xx
- ALTD
- AND (HL)
- AND HL,DE
- BIT b,(HL)
- CP (IX+d)
- DEC (HL)
- EX (SP),HL
- EX AF,AF
- INC (HL)
- IPSET
- IPRES
- LCALL x,mn
- LD (BC),A
- LD (HL+d),HL
- LD (IX+d),n
- LD (IY+d),n
- LD (mn),A
- LD (SP+n),HL
- LD A,(mn)
- LD A,IIR
- LD dd,(mn)
- LD dd,mn
- LD HL,(mn)
- LD HL,(SP+n)
- LD IX,(mn)
- LD IX,mn
- LD IY,(SP+n)
- LD r,(HL)
- LD SP,HL
- LDDR
- LDP (HL),HL
- LDP (mn),HL
- LDP HL,(HL)
- LDP HL,(mn)
- LJP x,mn
- OR (IY+d)
- OR HL,DE
- RES b,(HL)
- RETI
- RL (IX+d)
- RLC (HL)
- RLCA
- RR (IX+d)
- RRC (HL)
- RRCA
- SBC (IX+d)
- SBC HL,ss
- SET b,(HL)
- SLA (HL)
- SRA (HL)
- SRL (HL)
- SUB (HL)
- XOR (HL)
|
102 Rabbit 2000/3000 MicroprocessorDescriptionLogically shifts to the right the bits of the data whose address is• the data in word register HL, or• the sum of the data in index register IX and a displacement d, or• the sum of the data in index register IY and a displacement d.Each bit is shifted to the next lowest-order bit position (Bit 7 shifts to bit 6, etc.) Bit 0 shift to the Carry Flag,CF. Bit 7 is reset. See Figure 7 below.SRL (HL)SRL (IX+d)SRL (IY+d)Opcode Instruction Clocks OperationCB 3E SRL (HL) 10* (HL) = {0,(HL)[7,1]}; CF = (HL)[0]DD CB d 3E SRL (IX+d) 13** (IX + d) = {0,(IX + d)[7,1]};CF = (IX + d)[0]FD CB d 3E SRL (IY+d) 13** (IY + d) = {0,(IY + d)[7,1]};CF = (IY + d)[0]Clocking: *10 (2,2,1,2,3) **13 (2,2,2,2,2,3)Flags ALTD I/OS Z L/V C F R SP S D• • L • • • •Figure 7: The bit logic of the SRL instruction.
PreviousNext |