RadiSys Endura GL815E Product Manual

RadiSys Endura GL815E Product Manual Manual pdf 39 page image

GL815E Endura Motherboard Product ManualPage 39 of 51Address (hex)* DescriptionFFA0 – FFA7 Primary IDE bus master registersFFA8 – FFAF Secondary IDE bus master registersDynamically assigned USB controller (32 locations on 32-byte boundary)Dynamically assigned SMBus controller (16 locations on 16-byte boundary)Dynamically assigned PCI bridge (4096 locations on a 4096-byte boundary)Dynamically assigned LAN controller (32 locations on a 32-byte boundary)* An ‘x’ prefix for the address indicates that only the low-order 10 address bits are decoded.A.2. PCI Interrupt AllocationIn order to share PCI interrupts efficiently, the routing of the PCI interrupts INTA - INTD to themotherboard PCI interrupts PIRQA – PIRQD are rotated for each slot. Thus the PCI card INTAsignal for PCI slots 1 to 4 are spread across all four motherboard inputs. The Ethernet controllerand the second USB channel use additional motherboard PCI interrupts (PIRQE and PIRQH) thatare not routed to the slots. Interrupts PIRQF and PIRQG are not used and not available to the slots.Device PIRQA PIRQB PIRQC PIRQD PIRQE PIRQHSlot 1 (AGP4X) INTA INTB - - - -Slot 2 (PCI 2.2) INTD INTA INTB INTC - -Slot 3 (PCI 2.2) INTC INTD INTA INTB - -Slot 4 (PCI 2.2) INTB INTC INTD INTA - -Slot 5 (PCI 2.2) INTA INTB INTC INTD - -Slot 6 (PCI 2.2) INTD INTA INTB INTC - -VGA controller INTA - - - - -Ethernet controller - - - - INTA -USB controller 1 - - - INTD - -USB controller 2 - - - - - INTCSMBus controller - INTB - - - -AC97 audio controller - INTB - - - -Example. From the table above, the INTA interrupt from a card plugged into slot 2 would be routedto the motherboard PIRQB.