Sailor RE2100 Technical Manual

Also see for RE2100: Instruction book

Contents

Sailor RE2100 Technical Manual Manual pdf 113 page image

5 CIRCUIT DESCRIPTION AND SCHEMATIC DIAGRAMS RE2100PAGE 5-1394065.3 SYNTHESIZER UNIT (MODULE 3) PART NO. 625633The synthesizer unit consists of two phase locked loops. Phase locked loop 1 generates the signal usedas injection to the first mixer in the front end module and as the injection to the second mixer in the exciterunit. The PLL1 signal has a frequency range from 70 MHz to 100 MHz in steps of 10 Hz.Phase locked loop 2 generates the injection signal to the first mixer in the exciter unit and the injectionsignal to the second mixer in the receiver unit. The PLL2 signal changes between two frequencies 80.7MHz and 59.3 MHz when the transmitted or received sideband is changed between upper and lowersideband.PHASE LOCKED LOOP 1PLL1 operates as a fractional synthesizer. This means that the dividing figure in the loop can be set toa non-integer number, making it possible to get a frequency resolution at the VCO output which is smallerthan the reference frequency in the loop. The reference frequency is 40.96 kHz and the frequencyresolution is 10 Hz. The reference frequency is derived from a TCXO, which oscillates at 10.73152 MHz.Furthermore the TCXO signal is used as carrier signal for both detector in the receiver and SSB generatorin the exciter.The principle in a fractional synthesizer is that the integer number dividing figure N i in the loop is changedat particular times to (N i +1) determined by the value of fraction number F. By this method the meanfrequency of the VCO is increased as illustrated in the example below:fvco = N x frefi ifvco = (N + 0,25) x frefmeanT= 1frefifvco = (N + 1) x fref25740AIn the example the integer dividing figure is changed every fourth reference cycle implying an increasein mean VCO frequency.Because of the change in the integer number, dividing figure spurious sidebands occur at the VCO output.These sidebands have to be reduced and this is done through a correction signal fed to the phasedetector. The correction signal is generated in the API (Analog Phase Interpolator) circuit.VOLTAGE CONTROLLED OSCILLATORSThe frequency range from 70-100 MHz is covered with four independent oscillators:VCO I : 70 - 77.5 MHzVCO II : 77.5 - 85 MHzVCO III : 85 - 92.5 MHzVCO IV : 92.5 - 100 MHzThe oscillators are in principle identical and each of them is built-up around an earthed drain FET amplifier,where the output signal is fed back to the input by means of two capacitors. The ratio of the capacitorsdetermines the amount of feed-back in the oscillator. The oscillator frequency is determined by the LCcircuit located on the gate of the FET, and the tuning of oscillator frequency is done by means of variablecapacitance diodes.The output signal from the VCO’s is led through switch diodes D2, D5, D7, and D10 to a common bufferamplifier Q13, which buffers the VCO signal for prescaler buffer and LO buffer respectively.Selection of the wanted VCO circuit is done by Q1, Q3, Q4, Q6, Q7, Q9, Q10, and Q12. The control ofthese transistors is done by serial to parallel register U1.