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Samsung S5PC110 Manual
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Samsung S5PC110 Manual
Table of content
Contents
important notice
revision history
Table of Contents
Table Of Contents
Architectural Overview
Figure 1-1 S5PC110 Block Diagram
Microprocessor
Memory Subsystem
Multimedia
Audio Subsystem
Connectivity
System Peripheral
Conventions
Memory Map
Memory Address Map
CHIPID
Table of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Overview of CHIP ID
Register Description
General Purpose Input/ Output
Features
IO Driver strength
Input/ Output Description
Port Group GPA0 Control Register
Port Group GPA1 Control Register
Port Group GPB Control Register
Port Group GPC0 Control Register
Port Group GPC1 Control Register
Port Group GPD0 Control Register
Port Group GPD1 Control Register
Port Group GPE0 Control Register
Port Group GPE1 Control Register
Port Group GPF0 Control Register
Port Group GPF1 Control Register
Port Group GPF2 Control Register
Port Group GPF3 Control Register
Port Group GPG0 Control Register
Port Group GPG1 Control Register
Port Group GPG2 Control Register
Port Group GPG3 Control Register
Port Group GPI Control Register
Port Group GPJ0 Control Register
Port Group GPJ1 Control Register
Port Group GPJ2 Control Register
Port Group GPJ3 Control Register
Port Group GPJ4 Control Register
Port Group MP0_1 Control Register
Port Group MP0_2 Control Register
Port Group MP0_3 Control Register
Port Group MP0_4 Control Register
Port Group MP0_5 Control Register
Port Group MP0_6 Control Register
Port Group MP0_7 Control Register
Port Group MP1_0 Control Register
Port Group MP1_2 Control Register
Port Group MP1_4 Control Register
Port Group MP1_6 Control Register
Port Group MP1_8 Control Register
Port Group MP2_1 Control Register
Port Group MP2_3 Control Register
Port Group MP2_5 Control Register
Port Group MP2_7 Control Register
Port Group ETC0 Control Register
Port Group ETC1 Control Register
Port Group ETC2 Control Register
Port Group ETC3 is reserved
GPIO Interrupt Control Registers
Port Group GPH0 Control Register
Port Group GPH1 Control Register
Port Group GPH2 Control Register
Port Group GPH3 Control Register
External Interrupt Control Registers
Extern Pin Configuration Registers in Power down Mode
Clock Controller
Clock Declaration
Clocks from CMU
Clock Relationship
Recommended PLL PMS Value for APLL
Recommended PLL PMS Value for MPLL
Recommended PLL PMS Value for VPLL
Clock Generation
Table 3-5 Maximum Operating Frequency for Each Sub-block
Clock Configuration Procedure
Special Clock Description
Table 3-7 I/O Clocks in S5PC110
PLL Control Registers
Clock Source Control Registers
Clock Divider Control Register
Clock Gating Control Register
Clock Output Configuration Register
Figure 3-4 CLKOUT Waveform with DCLK Divider
Clock Divider Status SFRs
Clock MUX Status SFRs
Other SFRs
Miscellaneous SFRs
Power Management
FunctionAL Description of PMU
Table 4-2 S5PC110 Power Domains of Internal Logic
System Power Mode
Normal Mode
IDLE Mode
STOP Mode
DEEP-STOP Mode
SLEEP Mode
System Power Mode Transition
Figure 4-2 Internal Operation During Power Mode Transition
Transition Entering/ Exiting Condition
Cortex-A8 Power Mode
Figure 4-3 Cortex-A8 Power Mode Transition Diagram
State Save and Restore
Wakeup Sources
External Power Control
USB OTG PHY
MIPI D-PHY
Table 4-8 The Status of MPLL and SYSCLK After Wake-Up
ADC I/O
Internal memory control
Reset Control
Table 4-10 Register Initialization Due to Various Resets
Clock Control Register
Reset Control Register
Power Management Register
MISC Register
Intelligent Energy Management
Key Features of Intelligent Energy Management
Block Diagram
Functional Description of Intelligent Energy Management
IEM System Operation
IEM Implementation and Driver Setting
HPM Structure and Closed-Loop Behavior
Figure 5-5 IEM Closed-Loop Control Flow in APC1 HPM Delay
Figure 5-6 HPM Delay Tap structure in S5PC110
Initialization Sequence
I/O Description
IEC Related Registers
APC1 Related Registers
BOOTING SEQUENCE
Figure 6-1 Block Diagram of Booting Time Operation
Scenario Description
Booting Sequence Example
Fixed PLL and Clock Setting
OM Pin Configuration
Secure Booting
Figure 6-3 Secure Booting Diagram
bus configuration
dma controller
pwm operation
watchdog timer
modes of operation
register map
address mapping
camera interface
external interface
data format
hardware overview
data flow
video dac
block diagram of audio subsystem
electrical data
Rev. 0.0, Jan.2009
S5PC110
RISC Microprocessor
Revision 1.00
February 2010
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©
2010
Samsung Electronics Co., Ltd. All rights reserved.
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