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S3F80JB
Samsung S3F80JB User Manual
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Samsung S3F80JB User Manual
Table of content
Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
S3C8/S3F8-Series Microcontrollers
Features
Block Diagram (32-pin package)
Block Diagram (44-pin package)
Pin Assignments
Pin Assignment Diagram (44-Pin QFP Package)
Pin Descriptions of 32-SOP
Pin Descriptions of 44-QFP
Pin Circuits
Pin Circuit Type 2 (Port 1, Port4, P3.4 and P3.5)
Pin Circuit Type 3 (P3.0)
Pin Circuit Type 4 (P3.1)
Pin Circuit Type 6 (nRESET)
Overview
Program Memory
Smart Option
Register Architecture
Internal Register File Organization
Register Page Pointer (PP)
Register Set1
Prime Register Space
Working Registers
Using the Register Pointers
Non-Contiguous 16-Byte Working Register Block
Register Addressing
Register File Addressing
Common Working Register Area (C0H–CFH)
Bit Working Register Addressing
Bit Working Register Addressing Example
System and User Stacks
Standard Stack Operations Using PUSH and POP
Register Addressing Mode (R)
Indirect Register Addressing Mode (IR)
Indirect Register Addressing to Program Memory
Indirect Working Register Addressing to Register File
Indirect Working Register Addressing to Program or Data Memory
Indexed Addressing Mode (X)
Indexed Addressing to Program or Data Memory with Short Offset
Indexed Addressing to Program or Data Memory
Direct Address Mode (DA)
Direct Addressing for Call and Jump Instructions
Indirect Address Mode (IA)
Relative Address Mode (RA)
Immediate Mode (IM)
Mapped Registers (Bank0, Set1)
Mapped Registers (Bank1, Set1)
Register Description Format
BTCON Basic Timer Control Register
CACON Counter A Control Register
CLKCON System Clock Control Register
CMOD Comparator Mode Register
CMPSEL Comparator Input Selection Register
EMT External Memory Timing Register
FLAGS System Flags Register
FMCON Flash Memory Control Register
FMSECH Flash Memory Sector Address Register (High Byte)
IMR Interrupt Mask Register
IPH Instruction Pointer (High Byte)
IPR Interrupt Priority Register
LVD Flag
P0CONL Port 0 Control Register (Low Byte)
P0INT Port 0 External Interrupt Enable Register
P0PND Port 0 External Interrupt Pending Register
P0PUR Port 0 Pull-up Resistor Enable Register
P1CONH Port 1 Control Register (High Byte)
P1CONL Port 1 Control Register (Low Byte)
P2CONH Port 2 Control Register (High Byte)
P2CONL Port 2 Control Register (Low Byte)
P2INT Port 2 External Interrupt Enable Register
P2PND Port 2 External Interrupt Pending Register
P3CON Port 3 Control Register
Each Function Description and Pin Assignment of P3CON in 42/44 Pin Package
P345CON Port3[4:5] Control Register
P4CON Port 4 Control Register
P4CONH Port 4 Control Register (High Byte)
P4CONL Port 4 Control Register (Low Byte)
PP Register Page Pointer
RP0 Register Pointer 0
SPL Stack Pointer (Low Byte)
SYM System Mode Register
T1CON Timer 1 Control Register
T2CON Timer 2 Control Register
Interrupt Types
S3F80JB Interrupt Structure
Interrupt Vector Addresses
S3F80JB Interrupt Vectors
Enable/Disable Interrupt Instructions (EI, DI)
Interrupt Processing Control Points
Peripheral Interrupt Control Registers
System Mode Register (SYM)
Interrupt Mask Register (IMR)
Interrupt Priority Register (IPR)
Interrupt Request Register (IRQ)
Interrupt Pending Function Types
Interrupt Source Polling Sequence
Generating interrupt Vector Addresses
Instruction Group Summary
Flags Register (FLAGS)
Flag Descriptions
Instruction Set Notation
Instruction Notation Conventions
Opcode Quick Reference
Condition Codes
Instruction Descriptions
ADC Add with carry
AND Logical AND
BAND Bit AND
BCP Bit Compare
BITC Bit Complement
BITR Bit Reset
BITS Bit Set
BTJRF Bit Test, Jump Relative on False
BTJRT Bit Test, Jump Relative on True
BXOR Bit XOR
CALL Call Procedure
CCF Complement Carry Flag
CLR Clear
COM Complement
CP Compare
CPIJE Compare, Increment, and Jump on Equal
CPIJNE Compare, Increment, and Jump on Non-Equal
DA Decimal Adjust
DEC Decrement
DECW Decrement Word
DIV Divide (Unsigned)
DJNZ Decrement and Jump if Non-Zero
EI Enable Interrupts
ENTER Enter
EXIT Exit
IDLE Idle Operation
INC Increment
INCW Increment Word
IRET Interrupt Return
JR Jump Relative
LDB Load Bit
LDC/LDE Load Memory
LDCI/LDEI Load Memory and Increment
LDCPI/LDEPI Load Memory with Pre-Increment
LDW Load Word
MULT Multiply (Unsigned)
NEXT Next
NOP No Operation
OR Logical OR
POP Pop From Stack
POPUD Pop User Stack (Decrementing)
POPUI Pop User Stack (Incrementing)
PUSH Push To Stack
PUSHUD Push User Stack (Decrementing)
PUSHUI Push User Stack (Incrementing)
RCF Reset Carry Flag
RET Return
RL Rotate Left
RLC Rotate Left Through Carry
RR Rotate Right
RRC Rotate Right Through Carry
SB0 Select Bank 0
SB1 Select Bank 1
SBC Subtract With Carry
SCF Set Carry Flag
SRA Shift Right Arithmetic
STOP Stop Operation
SUB Subtract
SWAP Swap Nibbles
TCM Test Complement Under Mask
TM Test Under Mask
WFI Wait For Interrupt
XOR Logical Exclusive OR
System Clock Circuit
Clock Status During Power-Down Modes
System Clock Control Register (CLKCON)
Reset Sources
RESET Sources of The S3F80JB
RESET Block Diagram of The S3F80JB
Reset Mechanism
Internal Power-On Reset
Timing Diagram for Internal Power-On Reset Circuit
External Interrupt Reset
Stop Error Detection & Recovery
Power-Down Modes
Back-up mode
Stop Mode
Sources to Release Stop Mode
System Reset Operation
Hardware Reset Values
Set 1, Bank 1 Register Values After Reset
Reset Generation According to the Condition of Smart Option
Recommendation for Unusued Pins
Summary Table of Back-Up Mode, Stop Mode, and Reset Status
S3F80JB Port Configuration Overview (44-QFP)
S3F80JB Port Configuration Overview (32-SOP)
Port Data Registers
Pull-Up Resistor Enable Registers
Basic Timer (BT)
Basic Timer Control Register (BTCON)
Basic Timer Function Description
Timer 0 Control Register (T0CON)
Timer 0 DATA Register (T0DATA)
Timer 0 Function Description
Simplified Timer 0 Function Diagram: PWM Mode
Simplified Timer 0 Function Diagram: Capture Mode
Basic Timer and Timer 0 Block Diagram
Configuring the Basic Timer
Programming Timer 0
Timer 1 Overflow interrupt
Timer 1 Match interrupt
Timer 1 Block Diagram
Timer 1 Control Register (T1CON)
Timer 1 Registers (T1CNTH, T1CNTL, T1DATAH, T1DATAL)
Counter A Block Diagram
Counter A Control Register (CACON)
Counter A Pulse Width Calculations
Counter A Output Flip-Flop Waveforms in Repeat Mode
To Generate 38 kHz, 1/3duty Signal Through P3.1
To Generate a one Pulse Signal Through P3.1
Timer 2 Overflow Interrupt
Timer 2 Match Interrupt
Timer 2 Block Diagram
Timer 2 Control Register (T2CON)
Timer 2 Registers (T2CNTH, T2CNTL, T2DATAH, T2DATAL)
Comparator Block Diagram for The S3F80JB
Comparator Operation
Comparator Mode Register (CMOD)
Comparator Result Register (CMPREG)
Descriptions of Pins Used to Read/Write the Flash in Tool Program Mode
Program Memory Address Space
ISP Reset Vector and ISP Sector Size
Flash Memory Control Registers (User Program Mode)
Flash Memory Sector Address Registers
Sector Erase
Sector Erase Flowchart in User Program Mode
Programming
Byte Program Flowchart in a User Program Mode
Program Flowchart in a User Program Mode
Reading
Hard Lock Protection
Low Voltage Detector Control Register (LVDCON)
Typical Low-Side Driver (Sink) Characteristics (P3.1 only)·······································
Typical High-Side Driver (Source) Characteristics (P3.1 only)··································
Typical High-Side Driver (Source) Characteristics (P3.0 and P2.0-2.3)····················
Stop Mode Release Timing When Initiated by an External Interrupt·························
Stop Mode Release Timing When Initiated by a LVD ···············································
Input Timing for External Interrupts (Port 0 and Port 2) ············································
Pin SOP Package Dimension
Pin QFP Package Dimension
Target Boards
TB80JB Target Board
OTP/MTP Programmer (Writer)
important note
S3F80JB
8-BIT CMOS
MICROCONTROLLERS
USER'S MANUAL
Revision 1.1
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