Sanyo LED-DP32242 Service Manual

Also see for DP46142: Owner's manual Manual del propietario

Contents

25• Excellent (110%) over modulation at all white signal (100IRE)• Digital video IF AGC and optional delayed tuner AGC with programmable take over point• AM interference rejection•BTSC/A2 demodulator• BTSC mono, stereo and SAP DBX decoding for US NTSC TV reception• A2 mono, stereo and bilingual decoding for Korea NTSC TV reception• TS demultiplexer• Maximum transport bitrate: 80 Mbit/sec• ISO-13818-1 compliant• Supports PID filtering - total number of simultaneous PID filters: 32• ATSC-compliant transport demultiplexer• Maximum filtered (output) demux bit rate of 80 Mbits/sec• PCR locking using internal STC counter and VCXO control• Demodulator inputs• One (1) differential IF pair for all tuner formats• One (1) SIF (sound IF) for audio-only formats1.2.8. Memory Support• 16-bit DDR2 interface (400MHz or 475 MHz)• Up to 1.87 GByte/second peak memory throughput- 400MHz DDR2 sufficient for WXGA designs- 400MHz DDR2 sufficient for 1080p designs without TCON/overdrive- 533MHz DDR2 (clocked at 475MHz) sufficient for 1080p designs with TCON/overdrive• Up to 128 MBytes maximum memory- Typical 64MByte system implementation for WXGA and 1080p designs• High performance arbiter with assignable client priorities• SSTL-18 Class 1 electrical interface• Serial FLASH• 40MHz SPI clock• Up to 16 MBytes maximum memory• Typical 2-4 MByte system implementation1.2.9. Integrated TV MicroController• Support for “Sleep” mode operation• Front panel I/O support (buttons and display)