Xilinx KC705 User Manual

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Xilinx KC705 User Manual Manual pdf 18 page image

18 www.xilinx.com KC705 Evaluation BoardUG810 (v1.6.2) August 26, 2015Chapter 1: KC705 Evaluation Board FeaturesThe KC705 DDR3 SODIMM interface adheres to the constraints guidelines documented inthe DDR3 Design Guidelines section of 7 Series FPGAs Memory Interface SolutionsUser Guide (UG586) [Ref 3]. The KC705 DDR3 SODIMM interface is a 40Ω impedanceimplementation. Other memory interface details are available in UG586 and7 Series FPGAs Memory Resources User Guide (UG473) [Ref 4]. For more information aboutthe Micron MT8JTF12864HZ-1G6G1 part, see [Ref 5].Linear BPI Flash Memory[Figure 1-2, callout 3]The Linear BPI flash memory located at U58 provides 128 MB of nonvolatile storage thatcan be used for configuration or software storage. The data, address, and control signalsare connected to the FPGA. The BPI flash memory device is packaged in a 64-pin BGA.• Part number: PC28F00AP30TF (Micron)• Supply voltage: 2.5V• Datapath width: 16 bits (26 address lines and 7 control signals)• Data rate: Up to 33 MHzThe Linear BPI flash memory can synchronously configure the FPGA in Master BPI modeat the 33 MHz data rate supported by the PC28F00AP30TF flash memory by using aconfiguration bitstream generated with BitGen options for synchronous configuration andfor configuration clock division. The fastest configuration method uses the external66 MHz oscillator connected to the FPGA EMCCLK pin with a bitstream that has beenbuilt to divide the configuration clock by two. The division is necessary to remain withinthe synchronous read timing specifications of the flash memory.Multiple bitstreams can be stored in the Linear BPI flash memory. The two most significantaddress bits (A25, A24) of the flash memory are connected to DIP switch SW13 positions 1and 2 respectively, and to the RS1 and RS0 pins of the FPGA. By placing valid XC7K325Tbitstreams at four different offset addresses in the flash memory, 1 of the 4 bitstreams canbe selected to configure the FPGA by appropriately setting the DIP switch SW13. Theconnections between the BPI flash memory and the FPGA are listed in Table 1-5.AD9 DDR3_RAS_B SSTL15 110 RAS_BAF10 DDR3_CKE0 SSTL15 73 CKE0AE10 DDR3_CKE1 SSTL15 74 CKE1AH10 DDR3_CLK0_N DIFF_SSTL15 103 CK0_NAG10 DDR3_CLK0_P DIFF_SSTL15 101 CK0_PAF11 DDR3_CLK1_N DIFF_SSTL15 104 CK1_NAE11 DDR3_CLK1_P DIFF_SSTL15 102 CK1_PTable 1-4: DDR3 Memory Connections to the FPGA (Cont’d)U1 FPGA Pin Net Name I/O Standard J1 DDR3 MemoryPin Number Pin NameSend Feedback