Xilinx KC705 User Manual

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Xilinx KC705 User Manual Manual pdf 73 page image

KC705 Evaluation Board www.xilinx.com 73UG810 (v1.6.2) August 26, 2015Configuration OptionsConfiguration OptionsThe FPGA on the KC705 board can be configured by the following methods:• Master BPI (uses the Linear BPI flash memory)• Master SPI (uses the Quad SPI flash memory)• JTAG (uses the USB-to-JTAG Bridge or Download cable). See USB JTAG Module,page 24 for more informationSee 7 Series FPGAs Configuration User Guide (UG470) [Ref 2] for details on configurationmodes.The method used to configure the FPGA is controlled by the mode pin (M2, M1, M0)settings selected through DIP switch SW13. Table 1-35 lists the supported mode switchsettings.Figure 1-39 shows mode switch SW13.The mode pins settings on SW13 determine if the Linear BPI or the Quad SPI flash memoryis used for configuring the FPGA. DIP switch SW13 also provides the upper two addressbits for the Linear BPI flash memory and can be used to select one of multiple storedconfiguration bitstreams. Figure 1-40 shows the connectivity between the onboardnonvolatile flash devices used for configuration and the FPGA.Table 1-35: Mode Switch SW13 SettingsConfiguration Mode Mode Pins (M[2:0]) Bus Width CCLK DirectionMaster SPI 001 x1, x2, x4 OutputMaster BPI 010 x8, x16 OutputJTAG 101 x1 Not ApplicableX-Ref Target - Figure 1-39Figure 1-39: Mode SwitchUG810_c1_39_031214SDA05H1SBDSW13R401220Ω0.1 W1%R402220Ω0.1 W1%VCC2V5FPGA_M2FPGA_M1FPGA_M0FLASH_A25FLASH_A24R3961.21kΩ0.1 W1%R3971.21kΩ0.1 W1%R3981.21kΩ0.1 W1%R3991.21kΩ0.1 W1%R4001.21kΩ0.1 W1%12345109876GNDONSend Feedback