Xilinx Kintex-7 FPGA KC724 User Manual

Also see for Kintex-7 FPGA KC705: Getting started guide Getting started guide Getting started

20 www.xilinx.com KC724 GTX Transceiver Characterization BoardUG932 (v2.2) October 10, 2014Chapter 1: KC724 Board Features and Operation200 MHz 2.5V LVDS OscillatorU35 (callout 20, Figure 1-2).The KC724 board has one 200 MHz 2.5V LVDS oscillator (U35) connected to multi-regionclock capable (MRCC) inputs on the FPGA. Table 1-6 lists the FPGA pin connections to theLVDS oscillator.Differential SMA MRCC Pin InputsCallout 21, Figure 1-2.The KC724 board provides two pairs of differential SMA transceiver clock inputs that canbe used for connecting to an external function generator. The FPGA MRCC pins areconnected to the SMA connectors as shown in Table 1-7.SuperClock-2 ModuleCallout 22, Figure 1-2.The SuperClock-2 module connects to the clock module interface connector (J82) andprovides a programmable, low-noise and low-jitter clock source for the KC724 board. Theclock module maps to FPGA I/O by way of 24 control pins, 3 LVDS pairs, 1 regional clockpair, and 1 reset pin. Table 1-8 shows the FPGA I/O mapping for the SuperClock-2 moduleinterface. The KC724 board also supplies UTIL_5V0, UTIL_3V3, UTIL_2V5 and VCCO_HRinput power to the clock module interface.Table 1-6: LVDS Oscillator MRCC ConnectionsFPGA (U1) Schematic NetNameDevice (U35)Pin Function Direction IOSTANDARD Pin Function DirectionC25 SYSTEM CLOCK_P Input LVDS LVDS_OSC_P 4 200 MHz LVDS oscillator OutputB25 SYSTEM CLOCK_N Input LVDS LVDS_OSC_N 5 201 MHz LVDS oscillator OutputTable 1-7: Differential SMA Clock ConnectionsFPGA (U1) Schematic Net Name SMA ConnectorPin Function Direction IOSTANDARDAG29 USER CLOCK_1_P Input LVDS_25 CLK_DIFF_1_P J99AH29 USER CLOCK_1_N Input LVDS_25 CLK_DIFF_1_N J100D17 USER CLOCK_2_P Input LVDS_25 CLK_DIFF_2_P J98D18 USER CLOCK_2_N Input LVDS_25 CLK_DIFF_2_N J101Table 1-8: SuperClock-2 FPGA I/O MappingFPGA (U1) Schematic NetNameJ82 PinPin Function Direction IOSTANDARD Pin Function DirectionF11 Clock recovery Input LVDS_25 CM_LVDS1_P 1 Clock recovery OutputE11 Clock recovery Input LVDS_25 CM_LVDS1_N 3 Clock recovery OutputC12 Clock recovery Input LVDS_25 CM_LVDS2_P 9 Clock recovery OutputSend Feedback