70 MicroBlaze Development Kit Spartan-3E 1600 Edition User Guidewww.xilinx.com UG257 (v1.1) December 5, 2007Chapter 9: Digital to Analog Converter (DAC) RInterface SignalsTable 9-1 lists the interface signals between the FPGA and the DAC. The SPI_MOSI,SPI_MISO, and SPI_SCK signals are shared with other devices on the SPI bus. TheDAC_CS signal is the active-Low slave select input to the DAC. The DAC_CLR signal isthe active-Low, asynchronous reset input to the DAC.The serial data output from the DAC is primarily used to cascade multiple DACs. Thissignal can be ignored in most applications although it does demonstrate full-duplexcommunication over the SPI bus.Disable Other Devices on the SPI Bus to Avoid ContentionThe SPI bus signals are shared by other devices on the board. It is vital that other devicesare disabled when the FPGA communicates with the DAC to avoid bus contention.Table 9-2 provides the signals and logic values required to disable the other devices.Figure 9-2: Digital-to-Analog Connection SchematicsHeader J5DAC A12DAC B12DAC C1212SPI_MOSIDAC_CSSPI_SCKDAC_CLRCS/LDSDISCKCLRSDOSPI_MISO(N10) (T4)(U16)(P8)(N8)3.3V2.5VABCDGNDVCCREF AREF BREF CREF DVOUTAVOUTBVOUTCVOUTDSpartan-3E FPGADAC DLTC 2624 DACSPI Control Interface (3.3V)UG257_09_02_060606Table 9-1: DAC Interface SignalsSignal FPGA Pin Direction DescriptionSPI_MOSI T4 FPGAÆDAC Serial data: Master Output, Slave InputDAC_CS N8 FPGAÆDAC Active-Low chip-select. Digital-to-analogconversion starts when signal returns High.SPI_SCK U16 FPGAÆDAC ClockDAC_CLR P8 FPGAÆDAC Asynchronous, active-Low reset inputSPI_MISO N10 FPGAÅDAC Serial data: Master Input, Slave Output
