MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide 81UG257 (v1.1) December 5, 2007 www.xilinx.comDisable Other Devices on the SPI Bus to Avoid ContentionRDisable Other Devices on the SPI Bus to Avoid ContentionThe SPI bus signals are shared by other devices on the board. It is vital that other devicesare disabled when the FPGA communicates with the AMP or ADC to avoid buscontention. Table 10-4 provides the signals and logic values required to disable the otherdevices. Although the StrataFlash PROM is a parallel device, its least-significant data bit isshared with the SPI_MISO signal. The Platform Flash PROM is only potentially enabled ifthe FPGA is set up for Master Serial mode configuration.Connecting Analog InputsConnect AC signals to VINA or VINB via a DC blocking capacitor.Related Resourcesx Amplifier and A/D Converter Control for the Spartan-3E Starter Kit (ReferenceDesign)x http://www.xilinx.com/sp3e1600ex Xilinx PicoBlaze Soft Processorx http://www.xilinx.com/picoblazex LTC6912 Dual Programmable Gain Amplifiers with Serial Digital Interfacex http://www.linear.com/pc/downloadDocument.do?navId=H0,C1,C1154,C1009,C1121,P7596,D5359x LTC1407A-1 Serial 14-bit Simultaneous Sampling ADCs with Shutdownx http://www.linear.com/pc/downloadDocument.do?navId=H0,C1,C1155,C1001,C1158,P2420,D1295Figure 10-8: UCF Location Constraints for the ADC InterfaceNET "AD_CONV" LOC = "P11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;NET "SPI_SCK" LOC = "U16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;NET "SPI_MISO" LOC = "N10" | IOSTANDARD = LVCMOS33 ;UG257_10_08_061406Table 10-4: Disable Other Devices on SPI BusSignal Disabled Device Disable ValueSPI_SS_B SPI Serial Flash 1AMP_CS Programmable Pre-Amplifier 1DAC_CS DAC 1SF_CE0 StrataFlash Parallel Flash PROM 1FPGA_INIT_B Platform Flash PROM 1
