Xilinx SP605 User Manual

Also see for SP605: Hardware Tutorial Hardware setup guide Hardware user's guide

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Xilinx SP605 User Manual Manual pdf 33 page image

SP605 Hardware User Guide www.xilinx.com 33UG526 (v1.1.1) February 1, 2010Detailed Description12. USB-to-UART BridgeThe SP605 contains a Silicon Labs CP2103GM USB-to-UART bridge device (U4) whichallows connection to a host computer with a USB cable. The USB cable is supplied in thisevaluation kit (Type A end to host computer, Type Mini-B end to SP605 connector J23).Table 1-16 details the SP605 J23 pinout.Xilinx UART IP is expected to be implemented in the FPGA fabric (for instance, Xilinx XPSUART Lite). The FPGA supports the USB-to-UART bridge using four signal pins: Transmit(TX), Receive (RX), Request to Send (RTS), and Clear to Send (CTS).Silicon Labs provides royalty-free Virtual COM Port (VCP) drivers which permit theCP2103GM USB-to-UART bridge to appear as a COM port to host computercommunications application software (for example, HyperTerm or TeraTerm). The VCPdevice driver must be installed on the host PC prior to establishing communications withthe SP605. Refer to the evaluation kit Getting Started Guide for driver installationinstructions.ReferencesRefer to the Silicon Labs website for technical information on the CP2103GM and the VCPdrivers.In addition, see some of the Xilinx UART IP specifications at:• http://www.xilinx.com/support/documentation/ip_documentation/xps_uartlite.pdf• http://www.xilinx.com/support/documentation/ip_documentation/xps_uart16550.pdfTable 1-16: USB Type B Pin Assignments and Signal DefinitionsUSB ConnectorPin Signal Name Description1 VBUS +5V from host system (not used)2 USB_DATA_N Bidirectional differential serial data (N-side)3 USB_DATA_P Bidirectional differential serial data (P-side)4 GROUND Signal groundTable 1-17: USB-to-UART ConnectionsU1 FPGA Pin UART Functionin FPGASchematic NetNameU30 CP2103GMPinUART Functionin CP2103GMF18 RTS, output USB_1_CTS 22 CTS, inputF19 CTS, input USB_1_RTS 23 RTS, outputB21 TX, data out USB_1_RX 24 RXD, data inH17 RX, data in USB_1_TX 25 TXD, data outNotes:1. The schematic net names correspond with the CP2103GM pin names and functions, and the UART IPin the FPGA must be connected accordingly.