Xilinx Spartan-6 FPGA Series manuals
Spartan-6 FPGA Series
Table of contents
- revision history
- Table Of Contents
- Guide Contents
- Online Document
- Overview
- Features
- Block Diagram
- Detailed Description
- Spartan-6 XC6SLX16-2CSG324 FPGA
- MB DDR2 Component Memory
- SPI x4 Flash
- Linear Flash BPI
- Tri-Speed Ethernet PHY
- USB-to-UART Bridge
- Kb NV Memory
- Oscillator Socket (Single-Ended, 2.5V or 3.3V)
- Status LEDs
- FPGA Awake LED and Suspend Jumper
- FPGA INIT and DONE LEDs
- User I/O
- FPGA_PROG_B Pushbutton Switch
- Configuration Options
Spartan-6 FPGA Series
Table of contents
- revision history
- Table Of Contents
- Table Of Contents
- Guide Contents
- Additional Support Resources
- Overview
- Features
- Block Diagram
- Related Xilinx Documents
- Spartan-6 XC6SLX45T-3FGG484 FPGA
- I/O Voltage Rails
- SPI x4 Flash
- Linear BPI Flash
- FPGA Design Considerations for the Configuration Flash
- USB JTAG
- Clock Generation
- Oscillator Socket (Single-Ended, 2.5V or 3.3V)
- SMA Connectors (Differential)
- PCI Express Endpoint Connectivity
- SFP Module Connector
- Tri-Speed Ethernet PHY
- USB-to-UART Bridge
- DVI CODEC
- Kb NV Memory
- Status LEDs
- Ethernet PHY Status LEDs
- FPGA INIT and DONE LEDs
- User I/O
- User Pushbutton Switches
- User DIP Switch
- User SIP Header
- User SMA GPIO
- Switches
- FPGA_PROG_B Pushbutton SW3 (Active-Low)
- System ACE CF CompactFlash Image Select DIP Switch S1 (Active-High)
- Mode DIP Switch SW1 (Active-High)
- VITA 57.1 FMC LPC Connector
- Power Management
- Onboard Power Regulation
- Configuration Options
- for more information
Spartan-6 FPGA Series
Table of contents
- Revision History
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Guide Contents
- Additional Support Resources
- PCB Structures
- Vias
- Transmission Lines
- Return Currents
- PCB Decoupling Capacitors
- Required PCB Capacitor Quantities
- Capacitor Specifications
- Capacitor Consolidation Rules
- Ceramic Capacitor
- Basic PDS Principles
- Role of Inductance
- PCB Current Path Inductance
- Plane Inductance
- FPGA Mounting Inductance
- PCB Stackup and Layer Order
- Capacitor Effective Frequency
- Capacitor Anti-Resonance
- Power Supply Consolidation
- Simulation Methods
- PDS Measurements
- Noise Spectrum Measurements
- Optimum Decoupling Network Design
- Possibility 3: I/O Signals in PCB are Stronger Than Necessary
- Interface Types
- SDR versus DDR Interfaces
- How Fast is Fast
- Loss Tangent
- Traces
- Trace Routing
- Simulating Lossy Transmission Lines
- Excess Capacitance and Inductance
- BGA Package
- Differential Vias
- P/N Crossover Vias
- Configuration Modes
- Configuration Options
- MCB Clocking Considerations
- GTP Transceiver Clocking Considerations
- BUFIO2 I/O Clock Buffer Usage
- Overview of BUFIO2 Resource Usage per Interface Type
- Differential SerDes
- Density Migration
- Recommended PCB Design Rules for QFP Packages
- Recommended PCB Design Rules for BGA and CSP Packages
Spartan-6 FPGA Series
Table of contents
- Revision History
- Table Of Contents
- Table Of Contents
- Guide Contents
- Additional Support Resources
- Introduction
- Suspend Features
- Exiting Suspend Mode
- PROGRAM_B Programming Pin Always Overrides Suspend Mode
- Define the Multi-Pin Wake-Up Feature and Pins
- SUSPEND Attribute
- Design Requirements to Maintain Application Data
- Switch Outputs from Suspend to Normal Behavior
- SUSPEND Pin
- SUSPEND Input Glitch Filter
- Controlling Wake-Up from an External Source
- FPGA Voltage Requirements During Suspend Mode
- VCCINT
- VCCO
- VREF
- Lower-Power Spartan-6 LX Device Specifications
- Supply Sequencing
- Configuration Data Retention and Brown Out
- Forcing FPGA to Quiescent Current Levels
- Exiting Hibernate
- Saving Power
- Saving Clock Routing Power
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