Xilinx Virtex-4 FX FPGA User Manual
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Contents
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20 www.xilinx.com ML42x User GuideUG087 (v1.3) May 30, 2008Detailed Description RThe pin order in Table 15 is arranged from top to bottom as viewed on the board. It doesnot reflect the physical connection to this connector.57 AD16 AM22 AR2659 AC16 AM21 AP2661 AB15 AL19 AT2463 AA15 AL18 AR24Table 15: XGI Header (J11)Pin Number ML421 ML423 ML4241 IIC IIC IIC2 IIC IIC IIC3 U24 AG18 AP354 T24 AF18 AP345 Y16 AG16 AU266 Y15 AG17 AT267 W24 AF19 AT358 V24 AE17 AU359 AF14 AF21 AN2010 AF13 AE21 AP2011 AD15 AE16 AM2212 AD14 AF16 AN2213 AD13 AK29 AL1914 AC14 AJ29 AL2115 AC13 AK21 AK1916 AC12 AL21 AJ1917 AB12 AL29 AM2118 AA12 AM30 AM2019 TDO TDO TDO20 X TDO X TDO X TDO21 TCK TCK TCK22 TMS TMS TMS23 NC NC NC24 VCC3 VCC3 VCC325 VCC3 VCC3 VCC3Table 14: XGI Header (J13) (Continued)Pin Number ML421 ML423 ML424www.BDTIC.com/XILINX |
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