Xilinx Virtex-4 FX FPGA User Manual Manual pdf 5 page image
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Xilinx Virtex-4 FX FPGA User Manual

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Contents
  1. revision history
  2. Table Of Contents
  3. Additional Documentation
  4. Typographical Conventions
  5. Package Contents
  6. Related Documents
  7. Detailed Description
  8. Power Switch
  9. FPGA Configuration
  10. Oscillator Sockets
  11. Differential SMA Global Clocks
  12. User DIP Switches (Active-High)
  13. User Pushbutton Switches (Active-High)
  14. Xilinx Generic Interface
  15. LVDS Header Interface
  16. Program Switch (Active-Low)
  17. System ACE Controller
  18. RS-232 Port
  19. Table 23
Xilinx Virtex-4 FX FPGA User Manual Manual pdf 5 page image
ML42x User Guide www.xilinx.com 5UG087 (v1.3) May 30, 2008Preface: About This GuideML42x RocketIO Characterization PlatformTable 1: Platforms, Devices, and Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Table 2: Onboard Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Table 3: Power Supply Module Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Table 4: OSC Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Table 5: SMA Clock Pin Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Table 6: Differential SMA MGT Clock Pin Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . 15Table 7: Differential SMA Global Clock Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . 16Table 8: Differential SMA Regional Clock Pin Connections . . . . . . . . . . . . . . . . . . . . . . . 16Table 9: User LED, Row 1 (Top). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Table 10: User LED, Row 2 (Bottom). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Table 11: User DIP Switches, Row 1 (Top) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Table 12: User DIP Switches, Row 2 (Bottom) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Table 13: User Pushbutton Switches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Table 14: XGI Header (J13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Table 15: XGI Header (J11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20Table 16: XGI Header (J10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21Table 17: XGI Header (J14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21Table 18: LVDS Header (J139) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22Table 19: LVDS Header (J101) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24Table 20: Bitstream Address Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25Table 21: RocketIO Transceiver Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25Table 22: RS-232 Port Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29Table 23: System ACE Port Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30Schedule of Tableswww.BDTIC.com/XILINX
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Virtex-4 FX FPGA
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