Xilinx Virtex-II Pro User Manual
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Virtex-II Pro Prototype Platform User Guide www.xilinx.com 23UG027 / PN 0402044 (v1.6) October 25, 2002 1-800-255-7778User Programmable Pins RNotes:1. For proper operation of the SDRAM, use the LVCMOSDCI25 voltage standard on the FPGA pins.2. CS # is tied to the jumper labeled RAM_ENABLE/RAM_DISABLE.3. Disable the SDRAM when using the DUT pins as standard I/O pins.4. The SDRAM is a Samsung K4S64323LF-S(D)G/S75. For information on its operation, see:http://www.samsungelectronics.com/semiconductors/DRAM/Mobile_SDRAM/64M_bit/K4S64323LF/ds_k4s64323lf-s(d)g_s.pdfDQ27 E1 C2 K4DQ28 E3 C1 L7DQ29 D2 B1 K5DQ30 G2 F1 L1DQ31 D1 A2 F5A0 J4 R3 N3A1 J3 T3 N2A2 F4 P3 P2A3 F3 V3 AA4A4 G3 W2 AB3A5 G4 Y3 W5A6 K5 U1 AA1A7 G5 W3 Y9A8 P2 U3 AA6A9 L2 T2 Y3A10 H4 R2 R3DQM0 P3 V4 W6DQM1 M2 W1 AC1DQM2 H5 P4 L8DQM3 E4 V1 AA5RAS# J6 W4 W11CAS# M5 T4 R9WE# U3 U4 W7CKE L3 T1 Y1BA0 K6 R4 R10BA1 L4 P2 V11Table 1-11: SDRAM to FPGA Pin Mapping (Continued)SDRAM Pin FG456 FF672 FF1152 |
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