Xilinx Virtex-II Pro User Manual
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Contents
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Virtex-II Pro Prototype Platform User Guide www.xilinx.com 27UG027 / PN 0402044 (v1.6) October 25, 2002 1-800-255-7778RAppendix ARISCWatch and RISCTrace InterfacesThis appendix summarizes the interface requirements between the PPC405x3 and theRISCWatch and RISCTrace tools.The requirement for separate JTAG and trace connectors is being replaced with a singleMictor connector to improve the electrical and mechanical characteristics of the interface.Pin assignments for the Mictor connector are included in the signal-mapping tables.RISCWatch InterfaceThe RISCWatch tool communicates with the PPC405x3 using the JTAG and debuginterfaces. It requires a 16-pin, male 2x8 header connector located on the targetdevelopment board. The layout of the connector is shown in Figure A-1 and the signals aredescribed in Table A-1. A mapping of PPC405x3 to RISCWatch signals is provided inTable A-2. At the board level, the connector should be placed as close as possible to theprocessor chip to ensure signal integrity. Position 14 is used as a connection key and doesnot contain a pin.Figure A-1: JTAG-Connector Physical LayoutUG018_50_1009011511620.1"0.1" |
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