Xilinx Zynq UltraScale+ User Manual
Also see for ZCU106: User guideQuick start guidesManual
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Contents
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Zynq UltraScale+ VCU TRD User Guide 76UG1250 (v2019.1) May 29, 2019 www.xilinx.comChapter 5: Hardware PlatformInterrupt MapTable 5-6 shows interrupt ID mapping for the VCU TRD full-fledged design.Note: AXI Interrupt Controller used to accommodate all the interrupts as total number of PL-PSinterrupts exceeds 16 in the design.Table 5-7 shows interrupt ID mapping for VCU audio design.Table 5-6: Interrupt ID Map for Full-fledged DesignIP Core Interrupt IDHDMI CTL IIC 94HDMI Frame Buffer Read 89HDMI Frame Buffer Write_0 90HDMI Frame Buffer Write_1 108HDMI Frame Buffer Write_2 109HDMI RX 91HDMI TX 93Interrupt Controller 107MIPI Frame Buffer Write 105MIPI RX SS 104Sensor IIC 106TPG Frame Buffer Write 97VCU 96Video mixer 95Video Physical controller 92HDMI CTL IIC 94Table 5-7: Interrupt ID Map for VCU Audio DesignIP Core Interrupt IDHDMI I2C Controller 94HDMI 1.4/2.0 Transmitter Subsystem v2.0 93Video Mixer 92HDMI Frame Buffer Read 89HDMI Frame Buffer Write 90HDMI 1.4/2.0 Receiver Subsystem v2.0 91Audio Formatter MM2S 1 104Audio Formatter S2MM 1 105Send Feedback |
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