u-blox NINA-B112 System Integration Manual

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u-blox NINA-B112 System Integration Manual Manual pdf 35 page image

NINA-B1 series - System Integration ManualUBX-15026175 - R09 Design-inPage 35 of 493.6 General High Speed layout guidelinesThese general design guidelines are considered as best practices and are valid for any bus present in theNINA-B1 series modules; the designer should prioritize the layout of higher speed busses. Low frequency signalsare generally not critical for layout.One exception is represented by High Impedance traces (such as signals driven by weak pullresistors) that may be affected by crosstalk. For those traces, a supplementary isolation of 4w fromother busses is recommended.3.6.1 General considerations for schematic design and PCB floor-planning• Verify which signal bus requires termination and add series resistor terminations to the schematics.• Carefully consider the placement of the module with respect to antenna position and host processor.• Verify with PCB manufacturer allowable stack-ups and controlled impedance dimensioning.• Verify that the power supply design and power sequence are compliant with NINA-B1 series modulespecification (refer to section 1.3).3.6.2 Module placement• Accessory parts like bypass capacitors should be placed as close as possible to the module to improvefiltering capability, prioritizing the placement of the smallest size capacitor close to module pads.Particular care should be taken not to place components close to the antenna area. Thedesigner should carefully follow the recommendations from the antenna manufacturer about thedistance of the antenna vs. other parts of the system. The designer should also maximize the distanceof the antenna to Hi-frequency busses like DDRs and related components or consider an optionalmetal shield to reduce interferences that could be picked up by the antenna thus reducing themodule’s sensitivity.• An optimized module placement allows better RF performance. See Antenna interfaces section for moreinformation on antenna consideration during module placement.3.6.3 Layout and manufacturing• Avoid stubs on high speed signals. Even through-hole vias may have an impact on signal quality.• Verify the recommended maximum signal skew for differential pairs and length matching of buses.• Minimize the routing length; longer traces will degrade signal performance. Ensure that maximumallowable length for high speed busses is not exceeded.• Ensure that you track your impedance matched traces. Consult with your PCB manufacturer early in theproject for proper stack-up definition.• RF and digital sections should be clearly separated on the board.• Ground splitting is not allowed below the module.• Minimize bus length to reduce potential EMI issues from digital busses.• All traces (including low speed or DC traces) must couple with a reference plane (GND or power); Hi-speed busses should be referenced to the ground plane. In this case, if the designer needs to change theground reference, an adequate number of GND vias must be added in the area of transition to provide alow impedance path between the two GND layers for the return current.• Hi-Speed busses are not allowed to change reference plane. If a reference plane change is unavoidable,some capacitors should be added in the area to provide a low impedance return path through thedifferent reference planes.• Trace routing should keep a distance greater than 3w from the ground plane routing edge.• Power planes should keep a distance from the PCB edge sufficient to route a ground ring around thePCB, the ground ring must then be connected to other layers through vias.