Davicom DM9000 manuals
DM9000
Table of contents
- Table Of Contents
- Table Of Contents
- Features
- Pin Configuration
- Pin Configuration II: with 32-Bit Data Bus
- Pin Description
- Processor Interface
- Clock Interface
- Power Pins
- Vendor Control and Status Register Set
- Network Control Register (00H)
- TX Status Register I (03H)
- RX Status Register (06H)
- Flow Control Threshold Register (09H)
- ROM & PHY Address Register (0CH)
- Multicast Address Register (16H~1DH)
- Vendor ID Register (28H~29H)
- Memory Data Write Command with Address Increment Register (F8H)
- EEPROM Format
- MII Register Description
- Basic Mode Control Register (BMCR) – 00
- Basic Mode Status Register (BMSR) – 01
- PHY ID Identifier Register #1 (PHYID1) – 02
- Auto-negotiation Advertisement Register ANAR) – 04
- Auto-negotiation Link Partner Ability Register ANLPAR) – 05
- DAVICOM Specified Configuration Register DSCR) – 16
- DAVICOM Specified Configuration and Status Register (DSCSR) – 17
- Functional Description
- Base-TX Operation
- B5B Code Group
- Base-TX Receiver
- Code Group Alignment
- Power Reduced Mode
- DC and AC Electrical Characteristics
- DC Electrical Characteristics
- AC Electrical Characteristics & Timing Waveforms
- Processor Register Write Timing
- External MII Interface Transmit Timing
- MII Management Interface Timing
- Application Notes
- Magnetics Selection Guide
- Package Information
- Appendix
- Order Information
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