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Abov MC97F2664 manuals

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MC97F2664

Brand: Abov | Category: Microcontrollers
Table of contents
  1. Table Of Contents
  2. Table Of Contents
  3. Table Of Contents
  4. Table Of Contents
  5. Table Of Contents
  6. Table Of Contents
  7. Table Of Contents
  8. Overview
  9. Features
  10. Ordering Information
  11. Development Tools
  12. Figure 1.2 PGMplusUSB (Single Writer)
  13. Block Diagram
  14. Pin Assignment
  15. Figure 3.2 MC97F2664L14 64LQFP-1414 Pin Assignment
  16. Package Diagram
  17. Figure 4.2 64-Pin LQFP-1414 Package
  18. Figure 4.3 64-Pin QFN Package
  19. Figure 4.4 44-Pin MQFP-1010 Package
  20. Pin Description
  21. Port Structures
  22. External Interrupt I/O Port
  23. Electrical Characteristics
  24. A/D Converter Characteristics
  25. Power-On Reset Characteristics
  26. Internal RC Oscillator Characteristics
  27. DC Characteristics
  28. AC Characteristics
  29. SPI Characteristics
  30. UART Characteristics
  31. I2C Characteristics
  32. Data Retention Voltage in Stop Mode
  33. Internal Flash Rom Characteristics
  34. Main Clock Oscillator Characteristics
  35. Sub Clock Oscillator Characteristics
  36. Main Oscillation Stabilization Characteristics
  37. Operating Voltage Range
  38. Recommended Circuit and Layout
  39. Recommended Circuit and Layout with SMPS Power
  40. Typical Characteristics
  41. Figure 7.21 SUB RUN (IDD3) Current
  42. Figure 7.23 STOP (IDD5) Current
  43. Memory
  44. Figure 8.1 Program Memory
  45. Data Memory
  46. Figure 8.3 Lower 128 Bytes RAM
  47. XRAM Memory
  48. Table 8-1 SFR Map Summary
  49. Table 8-2 Extended SFR Map Summary
  50. Table 8-3 SFR Map
  51. Table 8-4 Extended SFR Map
  52. I/O Ports
  53. Table 9-1 Port Register Map
  54. P7 Port
  55. Interrupt Controller
  56. External Interrupt
  58. Interrupt Vector Table
  59. Interrupt Sequence
  60. Effective Timing after Controlling Interrupt Bit
  61. Multi Interrupt
  62. Interrupt Enable Accept Timing
  63. Interrupt Timing
  64. Interrupt Register Description
  65. Peripheral Hardware
  66. Table 11-1 Clock Generator Register Map
  67. Basic Interval Timer
  68. Table 11-2 Basic Interval Timer Register Map
  69. Watch Dog Timer
  70. Figure 11.4 Watch Dog Timer Block Diagram
  71. Watch Timer
  72. Table 11-4 Watch Timer Register Map
  73. Timer 0/1/2/3
  74. Figure 11.6 8-Bit Timer/Counter Mode for Timer 0/1/2/3 (Where n = 0, 1, 2, and 3)
  75. Figure 11.8 8-Bit PWM Mode for Timer 0/1/2/3 (Where n = 0, 1, 2, and 3)
  76. Figure 11.9 PWM Output Waveforms in PWM Mode for Timer 0/1/2 (Where n = 0, 1, 2, and 3)
  77. Figure 11.10 8-Bit Capture Mode for Timer 0/1/2/3 (Where n = 0, 1, 2, and 3)
  78. Figure 11.11 Input Capture Mode Operation for Timer 0/1/2/3 (Where n = 0, 1, 2, and 3)
  79. Figure 11.13 8-Bit Timer 0/1/2/3 Block Diagram (Where n = 0, 1, 2, and 3)
  80. Table 11-6 Timer 0/1/2/3 Register Map
  81. Timer 4/5
  82. Figure 11.14 16-Bit Timer/Counter Mode for Timer 4/5 ( where n= 4 and 5)
  83. Figure 11.16 16-Bit Capture Mode for Timer 4/5 ( where n= 4 and 5)
  84. Figure 11.17 Input Capture Mode Operation for Timer 4/5 ( where n= 4 and 5)
  85. Figure 11.19 16-Bit PPG Mode for Timer 4/5 ( where n= 4 and 5)
  86. Figure 11.20 16-Bit PPG Mode Timming chart for Timer 4/5 ( where n= 4 and 5)
  87. Figure 11.21 16-Bit Timer 4/5 Block Diagram ( where n= 4 and 5)
  88. Timer 6/7/8/9
  89. Figure 11.22 16-Bit Timer/Counter Mode for Timer 6/7/8/9 ( where n= 6,7,8, and 9)
  90. Figure 11.24 16-Bit Capture Mode for Timer 6/7/8/9 ( where n= 6,7,8, and 9)
  91. Figure 11.25 Input Capture Mode Operation for Timer 6/7/8/9 ( where n= 6,7,8, and 9)
  92. Figure 11.27 16-Bit PPG Mode for Timer 6/7/8/9 ( where n= 6,7,8, and 9)
  93. Figure 11.28 16-Bit PPG Mode Timming chart for Timer 6/7/8/9 ( where n= 6,7,8, and 9)
  94. Figure 11.29 16-Bit Timer 6/7/8/9 Block Diagram ( where n= 6,7,8, and 9)
  95. Buzzer Driver
  96. Table 11-12 Buzzer Driver Register Map
  97. SPI 2/3
  98. Figure 11.32 SPI 2/3 Transmit/Receive Timing Diagram at CPHA = 0 (Where n = 2 and 3)
  99. Table 11-13 SPI 2/3 Register Map
  100. UART2/3/4
  101. Figure 11.34 UART Block Diagram(where n = 2,3, and 4)
  102. Figure 11.35 Clock Generation Block Diagram (where n = 2,3, and 4)
  103. Figure 11.36 Frame Format
  104. Figure 11.37 Start Bit Sampling (where n = 2,3, and 4)
  105. Figure 11.39 Stop Bit Sampling and Next Start Bit Sampling (where n = 2,3, and 4)
  106. Table 11-16 Examples of UARTnBD Settings for Commonly Used Oscillator Frequencies
  107. USI0/1 (UART + SPI + I2C)
  108. Figure 11.40 USI0/1 UART Block Diagram (Where n = 0 and 1)
  109. Figure 11.41 Clock Generation Block Diagram (USIn, where n = 0 and 1)
  110. Figure 11.42 Synchronous Mode SCKn Timing (USIn , where n = 0 and 1)
  111. Figure 11.43 Frame Format (USI0/1)
  112. Figure 11.44 Asynchronous Start Bit Sampling (USIn, where n = 0 and 1)
  113. Figure 11.46 Stop Bit Sampling and Next Start Bit Sampling (USIn, where n = 0 and 1)
  114. Table 11-18 CPOLn Functionality (where n = 0 and 1)
  115. Figure 11.47 USI0/1 SPI Clock Formats when CPHAn=0 (where n = 0 and 1)
  116. Figure 11.48 USI0/1 SPI Clock Formats when CPHAn=1 (where n = 0 and 1)
  117. Figure 11.49 USI0/1 SPI Block Diagram (where n = 0 and 1)
  118. Figure 11.50 Bit Transfer on the I2C-Bus (USIn, where n = 0 and 1)
  119. Figure 11.51 START and STOP Condition (USIn, where n = 0 and 1)
  120. Figure 11.53 Acknowledge on the I2C-Bus (USIn, where n = 0 and 1)
  121. Figure 11.54 Clock Synchronization during Arbitration Procedure (USIn, where n = 0 and 1)
  122. Figure 11.56 Formats and States in the Master Transmitter Mode (USIn, where n = 0 and 1)
  123. Figure 11.57 Formats and States in the Master Receiver Mode (USIn, where n = 0 and 1)
  124. Figure 11.58 Formats and States in the Slave Transmitter Mode (USIn, where n = 0 and 1)
  125. Figure 11.59 Formats and States in the Slave Receiver Mode (USIn, where n = 0 and 1)
  126. Figure 11.60 USI0/1 I2C Block Diagram (where n = 0 and 1)
  127. Table 11-19 USI0/1 Register Map (where n = 0 and 1)
  128. Baud Rate setting (example)
  129. Bit A/D Converter
  130. Figure 11.61 12-bit ADC Block Diagram
  131. Figure 11.64 ADC Operation for Align Bit
  132. Figure 11.65 A/D Converter Operation Flow
  133. Power Down Operation
  134. IDLE Mode
  135. STOP Mode
  136. Release Operation of STOP Mode
  137. Table 12-2 Power Down Operation Register Map
  138. RESET
  139. RESET Noise Canceller
  140. Figure 13.5 Configuration Timing when Power-on
  141. Table 13-2 Boot Process Description
  142. External RESETB Input
  143. Brown Out Detector Processor
  144. LVI Block Diagram
  145. Table 13-3 Reset Operation Register Map
  146. On-chip Debug System
  147. Two-Pin External Interface
  148. Figure 14.3 Data Transfer on the Twin Bus
  149. Figure 14.5 Start and Stop Condition
  150. Figure 14.7 Clock Synchronization during Wait Procedure
  151. Figure 14.8 Connection of Transmission
  152. Flash Memory
  153. Figure 15.1 Flash Program ROM Structure
  154. Table 15-1 Flash Memory Register Map
  155. Configure Option
  156. APPENDIX
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