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AAC Microtec Sirius TCM manuals

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Sirius TCM

Brand: AAC Microtec | Category: Desktop
Table of contents
  1. revision log
  2. Table Of Contents
  3. Table Of Contents
  4. Table Of Contents
  5. Table Of Contents
  6. INTRODUCTION
  7. Reference documents
  8. EQUIPMENT INFORMATION
  9. Fault tolerant design
  10. SETUP AND OPERATION
  11. Connecting cables to the Sirius products
  12. Installation of toolchain
  13. Installing the Board Support Package (BSP)
  14. Setup a serial terminal to the device debug UART
  15. Loading an application
  16. Programming an application (boot image) to system flash
  17. Re-initialising the NVRAM
  18. RTEMS step-by-step compilation
  19. Software disclaimer of warranty
  20. Watchdog
  21. Usage description
  22. Error Manager
  23. status register
  24. Usage
  25. Limitations
  26. SCET
  27. RTEMS API
  28. UART
  29. Document number
  30. Data Structures
  31. Error injection
  32. Spacewire
  33. GPIO
  34. CCSDS
  35. Blocking
  36. Description
  37. NVRAM
  38. System flash
  39. Debug detect
  40. SPACEWIRE ROUTER
  41. SIRIUS TCM
  42. Block diagram
  43. Creating and writing a new configuration
  44. Fallback NVRAM parameters
  45. Telemetry
  46. Pulse commands
  47. Time Management
  48. Partition configuration
  49. Recovery
  50. ECSS standard services
  51. PUS-2 Distributing Device Command
  52. Spacewire RMAP
  53. Output
  54. Status code in reply messages
  55. RMAP output address details
  56. SYSTEM-ON-CHIP DEFINITIONS
  57. Interrupt sources
  58. Boot images and boot procedure
  59. SoC information map
  60. SOFTWARE UPLOAD
  61. CCSDS API – custom PUS service 130
  62. Subtype 1 – Image transfer start
  63. Subtype 3 – Verify uploaded image
  64. Subtype 5 – Calculate CRC in flash
  65. Software API
  66. int32_t swu_flash_check(...)
  67. TM/TC-STRUCTURE AND COP-1
  68. Randomization
  69. Transfer Frame Header
  70. Transfer Frame Data Field
  71. Frame Error Control Field
  72. Telemetry Format
  73. Transfer Frame Secondary Header
  74. Telemetry Packet Header
  75. Source Data
  76. UPDATING THE SIRIUS FPGA
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