MC96F6432June 22, 2018 Ver. 2.9 19711.12.3 USI0 UART Block DiagramRXD0 RxControlClockRecoveryReceive Shift Register(RXSR)DataRecoveryDOR0/PE0/FE0Checker USI0DR[0], USI0RX8[0], (Rx)USI0DR[1], USI0RX8[1], (Rx)TXD0 TxControlStop bitGeneratorParityGeneratorTransmit Shift Register(TXSR)USI0DR, USI0TX8, (Tx)USI0P[1:0]MUXLOOPS0TXC0TXCIE0 DRIE0DRE0Empty signalTo interruptblockINT_ACK ClearRXC0RXCIE0WAKEIE0WAKE0At Stop modeTo interruptblockSCLK(fx: System clock)Low leveldetector2USI0S[2:0]3USI0S[2:0]3TXE0RXE0DBLS0USI0SBBaud Rate GeneratorUSI0BDINTERNALBUSLINESCK0 ACKControlClockSync LogicMasterUSI0MS[1:0]MUXMUXUSI0MS[1:0]USI0MS[1:0]222Figure 11.57 USI0 UART Block Diagram
