Manuals database logo
manualsdatabase
Your AI-powered manual search engine

Abov MC96F6432 Series User Manual

Page 1 preview
Page 2 preview
Page 3 preview
Page 4 preview
Page 5 preview
Page 6 preview
Page 7 preview
Page 8 preview
Page 9 preview
Page 10 preview
Page 11 preview
Page 12 preview
Page 13 preview
Page 14 preview
Page 15 preview
Page 16 preview
Page 17 preview
Page 18 preview
Page 19 preview
Page 20 preview
Page 21 preview
Page 22 preview
Page 23 preview
Page 24 preview
Page 25 preview
Page 26 preview
Page 27 preview
Page 28 preview
Page 29 preview
Page 30 preview
Page 31 preview
Page 32 preview
Page 33 preview
Page 34 preview
Page 35 preview
Page 36 preview
Page 37 preview
Page 38 preview
Page 39 preview
Page 40 preview
Page 41 preview
Page 42 preview
Page 43 preview
Page 44 preview
Page 45 preview
Page 46 preview
Page 47 preview
Page 48 preview
Page 49 preview
Page 50 preview
Page 51 preview
Page 52 preview
Page 53 preview
Page 54 preview
Page 55 preview
Page 56 preview
Page 57 preview
Page 58 preview
Page 59 preview
Page 60 preview
Page 61 preview
Page 62 preview
Page 63 preview
Page 64 preview
Page 65 preview
Page 66 preview
Page 67 preview
Page 68 preview
Page 69 preview
Page 70 preview
Page 71 preview
Page 72 preview
Page 73 preview
Page 74 preview
Page 75 preview
Page 76 preview
Page 77 preview
Page 78 preview
Page 79 preview
Page 80 preview
Page 81 preview
Page 82 preview
Page 83 preview
Page 84 preview
Page 85 preview
Page 86 preview
Page 87 preview
Page 88 preview
Page 89 preview
Page 90 preview
Page 91 preview
Page 92 preview
Page 93 preview
Page 94 preview
Page 95 preview
Page 96 preview
Page 97 preview
Page 98 preview
Page 99 preview
Page 100 preview
Page 101 preview
Page 102 preview
Page 103 preview
Page 104 preview
Page 105 preview
Page 106 preview
Page 107 preview
Page 108 preview
Page 109 preview
Page 110 preview
Page 111 preview
Page 112 preview
Page 113 preview
Page 114 preview
Page 115 preview
Page 116 preview
Page 117 preview
Page 118 preview
Page 119 preview
Page 120 preview
Page 121 preview
Page 122 preview
Page 123 preview
Page 124 preview
Page 125 preview
Page 126 preview
Page 127 preview
Page 128 preview
Page 129 preview
Page 130 preview
Page 131 preview
Page 132 preview
Page 133 preview
Page 134 preview
Page 135 preview
Page 136 preview
Page 137 preview
Page 138 preview
Page 139 preview
Page 140 preview
Page 141 preview
Page 142 preview
Page 143 preview
Page 144 preview
Page 145 preview
Page 146 preview
Page 147 preview
Page 148 preview
Page 149 preview
Page 150 preview
Page 151 preview
Page 152 preview
Page 153 preview
Page 154 preview
Page 155 preview
Page 156 preview
Page 157 preview
Page 158 preview
Page 159 preview
Page 160 preview
Page 161 preview
Page 162 preview
Page 163 preview
Page 164 preview
Page 165 preview
Page 166 preview
Page 167 preview
Page 168 preview
Page 169 preview
Page 170 preview
Page 171 preview
Page 172 preview
Page 173 preview
Page 174 preview
Page 175 preview
Page 176 preview
Page 177 preview
Page 178 preview
Page 179 preview
Page 180 preview
Page 181 preview
Page 182 preview
Page 183 preview
Page 184 preview
Page 185 preview
Page 186 preview
Page 187 preview
Page 188 preview
Page 189 preview
Page 190 preview
Page 191 preview
Page 192 preview
Page 193 preview
Page 194 preview
Page 195 preview
Page 196 preview
Page 197 preview
Page 198 preview
Page 199 preview
Page 200 preview
Page 201 preview
Page 202 preview
Page 203 preview
Page 204 preview
Page 205 preview
Page 206 preview
Page 207 preview
Page 208 preview
Page 209 preview
Page 210 preview
Page 211 preview
Page 212 preview
Page 213 preview
Page 214 preview
Page 215 preview
Page 216 preview
Page 217 preview
Page 218 preview
Page 219 preview
Page 220 preview
Page 221 preview
Page 222 preview
Page 223 preview
Page 224 preview
Page 225 preview
Page 226 preview
Page 227 preview
Page 228 preview
Page 229 preview
Page 230 preview
Page 231 preview
Page 232 preview
Page 233 preview
Page 234 preview
Page 235 preview
Page 236 preview
Page 237 preview
Page 238 preview
Page 239 preview
Page 240 preview
Page 241 preview
Page 242 preview
Page 243 preview
Page 244 preview
Page 245 preview
Page 246 preview
Page 247 preview
Page 248 preview
Page 249 preview
Page 250 preview
Page 251 preview
Page 252 preview
Page 253 preview
Page 254 preview
Page 255 preview
Page 256 preview
Page 257 preview
Page 258 preview
Page 259 preview
Page 260 preview
Page 261 preview
Page 262 preview
Page 263 preview
Page 264 preview
Page 265 preview
Page 266 preview
Page 267 preview
Page 268 preview
Page 269 preview
Page 270 preview
Page 271 preview
Page 272 preview
Page 273 preview
Page 274 preview
Page 275 preview
Page 276 preview
Page 277 preview
Page 278 preview
Page 279 preview
Page 280 preview
Page 281 preview
Page 282 preview
Page 283 preview
Page 284 preview
Page 285 preview
Page 286 preview
Page 287 preview
Page 288 preview
Page 289 preview
Page 290 preview
Page 291 preview
Page 292 preview
Page 293 preview
Page 294 preview
Page 295 preview
Page 296 preview
Page 297 preview
Page 298 preview
Page 299 preview
Page 300 preview
Page 301 preview
Page 302 preview
Page 303 preview
Page 304 preview
Page 305 preview
Page 306 preview
Page 307 preview
Page 308 preview
Page 309 preview
Page 310 preview
Page 311 preview
Page 312 preview
Page 313 preview
Page 314 preview
Page 315 preview
Page 316 preview
Page 317 preview
Page 318 preview
Page 319 preview
Page 320 preview
Page 321 preview
Page 322 preview
Page 323 preview
Page 324 preview
Page 325 preview
Page 326 preview
Page 327 preview
Contents
  1. Table Of Contents
  2. Table Of Contents
  3. Table Of Contents
  4. Table Of Contents
  5. Table Of Contents
  6. Table Of Contents
  7. Table Of Contents
  8. Table Of Contents
  9. Overview
  10. Features
  11. Ordering Information
  12. Development Tools
  13. Figure 1.2 E-PGM+(Single writer)
  14. Figure 1.3 E-GANG4 and E-GANG6 (for Mass Production)
  15. Block Diagram
  16. Pin Assignment
  17. Figure 3.2 MC96F6432Q 44MQFP-1010 Pin Assignment
  18. Figure 3.3 MC96F6332L 32LQFP Pin Assignment
  19. Figure 3.4 MC96F6332D 32SOP Pin Assignment
  20. Package Diagram
  21. Figure 4.2 44-Pin MQFP Package
  22. Figure 4.3 32-Pin LQFP Package
  23. Figure 4.4 32-Pin SOP Package
  24. Figure 4.5 28-Pin SOP Package
  25. Pin Description
  26. Port Structures
  27. External Interrupt I/O Port
  28. Electrical Characteristics
  29. A/D Converter Characteristics
  30. Low Voltage Reset and Low Voltage Indicator Characteristics
  31. High Internal RC Oscillator Characteristics
  32. LCD Voltage Characteristics
  33. DC Characteristics
  34. AC Characteristics
  35. SPI0/1/2 Characteristics
  36. UART0/1 Characteristics
  37. I2C0/1 Characteristics
  38. Data Retention Voltage in Stop Mode
  39. Internal Flash Rom Characteristics
  40. Main Clock Oscillator Characteristics
  41. Sub Clock Oscillator Characteristics
  42. Main Oscillation Stabilization Characteristics
  43. Operating Voltage Range
  44. Recommended Circuit and Layout
  45. Recommended Circuit and Layout with SMPS Power
  46. Typical Characteristics
  47. Figure 7.19 SUB RUN (IDD3) Current
  48. Figure 7.21 STOP (IDD5) Current
  49. Memory
  50. Figure 8.1 Program Memory
  51. Data Memory
  52. Figure 8.3 Lower 128 Bytes RAM
  53. XRAM Memory
  54. Table 8-1 SFR Map Summary
  55. Table 8-2 SFR Map Summary
  56. Table 8-3 SFR Map
  57. I/O Ports
  58. Table 9-1 Port Register Map
  59. Port Function
  60. Interrupt Controller
  61. External Interrupt
  63. Interrupt Vector Table
  64. Figure 10.3 Interrupt Sequence Flow
  65. Effective Timing after Controlling Interrupt Bit
  66. Multi Interrupt
  67. Interrupt Enable Accept Timing
  68. Interrupt Timing
  69. Table 10-3 Interrupt Register Map
  70. Peripheral Hardware
  71. Table 11-1 Clock Generator Register Map
  72. Basic Interval Timer
  73. Table 11-2 Basic Interval Timer Register Map
  74. Watch Dog Timer
  75. Figure 11.4 Watch Dog Timer Block Diagram
  76. Watch Timer
  77. Table 11-4 Watch Timer Register Map
  78. Timer 0
  79. Figure 11.6 8-Bit Timer/Counter Mode for Timer 0
  80. Figure 11.8 8-Bit PWM Mode for Timer 0
  81. Figure 11.9 PWM Output Waveforms in PWM Mode for Timer 0
  82. Figure 11.10 8-Bit Capture Mode for Timer 0
  83. Figure 11.11 Input Capture Mode Operation for Timer 0
  84. Figure 11.13 8-Bit Timer 0 Block Diagram
  85. Table 11-6 Timer 0 Register Map
  86. Timer 1
  87. Figure 11.14 16-Bit Timer/Counter Mode for Timer 1
  88. Figure 11.16 16-Bit Capture Mode for Timer 1
  89. Figure 11.17 Input Capture Mode Operation for Timer 1
  90. Figure 11.19 16-Bit PPG Mode for Timer 1
  91. Figure 11.20 16-Bit PPG Mode Timming chart for Timer 1
  92. Figure 11.21 16-Bit Timer 1 Block Diagram
  93. Timer 2
  94. Figure 11.22 16-Bit Timer/Counter Mode for Timer 2
  95. Figure 11.23 16-Bit Timer/Counter 2 Example
  96. Figure 11.24 16-Bit Capture Mode for Timer 2
  97. Figure 11.25 Input Capture Mode Operation for Timer 2
  98. Figure 11.27 16-Bit PPG Mode for Timer 2
  99. Figure 11.28 16-Bit PPG Mode Timming chart for Timer 2
  100. Figure 11.29 16-Bit Timer 2 Block Diagram
  101. Timer 3,
  102. Figure 11.30 8-Bit Timer/Counter Mode for Timer 3, 4
  103. Figure 11.31 16-Bit Timer/Counter Mode for Timer 3
  104. Figure 11.32 8-Bit Capture Mode for Timer 3, 4
  105. Figure 11.33 16-Bit Capture Mode for Timer 3
  106. Table 11-12 PWM Frequency vs. Resolution at 8 MHz
  107. Figure 11.34 10-Bit PWM Mode (Force 6-ch)
  108. Figure 11.35 10-Bit PWM Mode (Force All-ch)
  109. Figure 11.36 Example of PWM at 4 MHz
  110. Figure 11.38 Example of PWM Output Waveform
  111. Figure 11.40 Example of Phase Correction and Frequency correction of PWM
  112. Figure 11.42 Example of Force Drive All Channel with A-ch
  113. Figure 11.43 Example of Force Drive 6-ch Mode
  114. Figure 11.44 Example of PWM Delay
  115. Figure 11.45 Two 8-Bit Timer 3, 4 Block Diagram
  116. Figure 11.46 16-Bit Timer 3 Block Diagram
  117. Table 11-14 Timer 3, 4 Register Map
  118. Buzzer Driver
  119. Table 11-16 Buzzer Driver Register Map
  120. Figure 11.49 SPI 2 Block Diagram
  121. Table 11-17 SPI 2 Register Map
  122. Bit A/D Converter
  123. Figure 11.52 12-bit ADC Block Diagram
  124. Figure 11.55 ADC Operation for Align Bit
  125. Figure 11.56 A/D Converter Operation Flow
  126. USI0 (UART + SPI + I2C)
  127. Figure 11.57 USI0 UART Block Diagram
  128. Figure 11.58 Clock Generation Block Diagram (USI0)
  129. Figure 11.59 Synchronous Mode SCK0 Timing (USI0)
  130. Figure 11.60 Frame Format (USI0)
  131. Figure 11.61 Asynchronous Start Bit Sampling (USI0)
  132. Figure 11.63 Stop Bit Sampling and Next Start Bit Sampling (USI0)
  133. Table 11-20 CPOL0 Functionality
  134. Figure 11.64 USI0 SPI Clock Formats when CPHA0=0
  135. Figure 11.65 USI0 SPI Clock Formats when CPHA0=1
  136. Figure 11.66 USI0 SPI Block Diagram
  137. Figure 11.67 Bit Transfer on the I2C-Bus (USI0)
  138. Figure 11.68 START and STOP Condition (USI0)
  139. Figure 11.70 Acknowledge on the I2C-Bus (USI0)
  140. Figure 11.71 Clock Synchronization during Arbitration Procedure (USI0)
  141. Figure 11.73 Formats and States in the Master Transmitter Mode (USI0)
  142. Figure 11.74 Formats and States in the Master Receiver Mode (USI0)
  143. Figure 11.75 Formats and States in the Slave Transmitter Mode (USI0)
  144. Figure 11.76 Formats and States in the Slave Receiver Mode (USI0)
  145. Figure 11.77 USI0 I2C Block Diagram
  146. Table 11-21 USI0 Register Map
  147. USI1 (UART + SPI + I2C)
  148. Figure 11.78 USI1 UART Block Diagram
  149. Figure 11.79 Clock Generation Block Diagram (USI1)
  150. Figure 11.80 Synchronous Mode SCK1 Timing (USI1)
  151. Figure 11.81 Frame Format (USI1)
  152. Figure 11.82 Asynchronous Start Bit Sampling (USI1)
  153. Figure 11.84 Stop Bit Sampling and Next Start Bit Sampling (USI1)
  154. Table 11-23 CPOL1 Functionality
  155. Figure 11.85 USI1 SPI Clock Formats when CPHA1=0
  156. Figure 11.86 USI1 SPI Clock Formats when CPHA1=1
  157. Figure 11.87 USI1 SPI Block Diagram
  158. Figure 11.88 Bit Transfer on the I2C-Bus (USI1)
  159. Figure 11.89 START and STOP Condition (USI1)
  160. Figure 11.91 Acknowledge on the I2C-Bus (USI1)
  161. Figure 11.92 Clock Synchronization during Arbitration Procedure (USI1)
  162. Figure 11.94 Formats and States in the Master Transmitter Mode (USI1)
  163. Figure 11.95 Formats and States in the Master Receiver Mode (USI1)
  164. Figure 11.96 Formats and States in the Slave Transmitter Mode (USI1)
  165. Figure 11.97 Formats and States in the Slave Receiver Mode (USI1)
  166. Figure 11.98 USI1 I2C Block Diagram
  167. Table 11-24 USI1 Register Map
  168. Table 11-25 Examples of USI0BD and USI1BD Settings for Commonly Used Oscillator Frequencies
  169. LCD Driver
  170. Figure 11.99 LCD Circuit Block Diagram
  171. Figure 11.100 LCD Signal Waveforms (1/2Duty, 1/2Bias)
  172. Figure 11.101 LCD Signal Waveforms (1/3Duty, 1/3Bias)
  173. Figure 11.102 LCD Signal Waveforms (1/4Duty, 1/3Bias)
  174. Figure 11.103 LCD Signal Waveforms (1/8Duty, 1/4Bias)
  175. Figure 11.104 Internal Resistor Bias Connection
  176. Figure 11.105 External Resistor Bias Connection
  177. Figure 11.106 LCD Circuit Block Diagram
  178. Table 11-27 LCD Frame Frequency
  179. Power Down Operation
  180. IDLE Mode
  181. STOP Mode
  182. Release Operation of STOP Mode
  183. Table 12-2 Power Down Operation Register Map
  184. RESET
  185. RESET Noise Canceller
  186. Figure 13.5 Configuration Timing when Power-on
  187. Table 13-2 Boot Process Description
  188. External RESETB Input
  189. Brown Out Detector Processor
  190. LVI Block Diagram
  191. Register Map
  192. On-chip Debug System
  193. Two-Pin External Interface
  194. Figure 14.3 Data Transfer on the Twin Bus
  195. Figure 14.5 Start and Stop Condition
  196. Figure 14.7 Clock Synchronization during Wait Procedure
  197. Figure 14.8 Connection of Transmission
  198. Flash Memory
  199. Figure 15.1 Flash Program ROM Structure
  200. Table 15-1Flash Memory Register Map
  201. Figure 15.2 Flow of Protection for Invalid Erase/Write
  202. Configure Option
  203. APPENDIX
Abov MC96F6432 Series User Manual Manual pdf 35 page image
MC96F6432June 22, 2018 Ver. 2.9 356.2 External Interrupt I/O PortPULL-UPREGISTER VDDVDDPADVDDOPEN DRAINREGISTERDATAREGISTERDIRECTIONREGISTERMUX01MUX10INTERRUPTENABLEEXTERNALINTERRUPTQ DCPrVDDFLAGCLEARPOLARITYREG.MUX10DEBOUNCEENABLEQ DCPr DEBOUNCECLKCMOS orSchmitt LevelInputANALOG CHANNELENABLEANALOG INPUTPORTx INPUT orSUB-FUNC DATA INPUTSUB-FUNC DIRECTIONSUB-FUNC ENABLESUB-FUNC DATA OUTPUTLevel Shift (ExtVDD to 1.8V)Level Shift (1.8V to ExtVDD)Figure 6.2 External Interrupt I/O Port
/ 327
Related manuals for Abov MC96F6332D
Abov MC96F6432S Series User Manual first page preview
Abov MC96F6432S Series User Manual
Abov MC96F6432A User Manual first page preview
Abov MC96F6432A User Manual
Abov MC96F8204 Series User Manual first page preview
Abov MC96F8204 Series User Manual
Abov MC96FR116C Series User Manual first page preview
Abov MC96FR116C Series User Manual
Abov MC95FG208 Series User Manual first page preview
Abov MC95FG208 Series User Manual
Abov MC96FM204 User Manual first page preview
Abov MC96FM204 User Manual
Abov MC96FR364B User Manual first page preview
Abov MC96FR364B User Manual
Abov MC97F2664 User Manual first page preview
Abov MC97F2664 User Manual
Abov MC97F6108A User Manual first page preview
Abov MC97F6108A User Manual
Abov MC97F60128 User Manual first page preview
Abov MC97F60128 User Manual
This manual is suitable for:
MC96F6332DMC96F6332LMC96F6332MMC96F6432 SeriesMC96F6432LMC96F6432Q
Manuals database logo
manualsdatabase
Your AI-powered manual search engine