MC96F6432242 June 22, 2018 Ver. 2.9The process for detecting stop bit is like clock and data recovery process. That is, if 2 or more samples of 3center values have high level, correct stop bit is detected, else a frame error (FE1) flag is set. After decidingwhether the first stop bit is valid or not, the Receiver goes to idle state and monitors the RXD1 line to check avalid high to low transition is detected (start bit detection).Figure 11.84 Stop Bit Sampling and Next Start Bit Sampling (USI1)RXD11 2 3 4 5 6 7 8 9 10 11 12 13STOP 11 2 3 4 5 6 7Sample(DBLS1 = 0)Sample(DBLS1 = 1)(A) (B) (C)
