1 System overview4MemoryThe four DIMM sockets on board accept 256-, 512-MB or 1-GB DDR(Double Data Rate) SDRAM for a maximum memory capacity of up to4 GB.For data integrity, the default setting for the ECC (error correctingcode) function of the memory system in BIOS is enabled.Note: The mainboard supports PC2100/DDR-266 SDRAM DIMMs.Refer to “Mainboard layout” on page 14 for the location of theseDIMM slots on the mainboard.System chipsetsServer Works chipsetThe Server Works GC-SL(Grand Champion – Super Lite) chipset isspecifically designed to meet the needs of high performance systems. Itconsists of the following components:• CMIC-SL (north bridge) is responsible for communication betweenthe processor, the memory bus, and the IMB (inter-module bus)bus. It runs directly to the processor bus at 133MHz and integratesthe functions of main memory controller for DDR. IMB interfaceunit runs at 400MHz and connects to CIOBX2, and one narrow-version of IMB (Thin-IMB) connects to South Bridge CSB5.• CIOBX2 (I/O bridge) is a peripheral chip that performs PCI bridgingfunction between the IMB and the 2 PCI-X buses.• CSB5 (south bridge) integrates the LPC interface that links superI/O functions like keyboard and mouse interface, floppy diskcontroller, advanced digital data separator, serial port, on-chip 12mA AT bus drivers, one floppy direct drive support, and IPM(intelligent power management) support.
