Acer TM7300 Series Service Manual

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Acer TM7300 Series Service Manual Manual pdf 109 page image

2-52Service Guide2.6.4 Pin DescriptionTable 2-6 NS97338VJG Pin DescriptionsPin No. I/O DescriptionA15-A0 67, 64,62-60,29, 19-28I Address. These address lines from the microprocessor determinewhich internal register is accessed. A0-A15 are don't cares duringDMA transfer./ACK 83 I Parallel Port Acknowledge. This input is pulsed low by the printer toindicate that it has received the data from the parallel port. This pinhas a nominal 25 KΩ pull-up resistor attached to it.ADRATE0,ADRATE196,46O FDD Additional Data Rate 0,1. These outputs are similar to DRATE0,1. They are provided in addition to DRATE0, 1. They reflect thecurrently selected FDC data rate, (bits 0 and 1 in the ConfigurationControl Register (CCR) or the Data Rate Select Register (DSR),whichever was written to last). ADRATE0 is configured when bit 0 ofASC is 1. ADRATE1 is configured when bit 4 of ASC is 1. (See IRQ5and DENSEL for further information)./AFD 76 I/O Parallel Port Automatic Feed XT. When this signal is low, the printerautomatically line feed after printing each line. This pin is in a tristatecondition 10 ns after a 0 is loaded into the corresponding ControlRegister bit. The system should pull this pin high using a 4.7 KΩresistor.AEN 18 I Address Enable. When this input is high, it disables function selectionvia A15-A0. Access during DMA transfer is not affected by this pin./ASTRB 79 O EPP Address Strobe. This signal is used in EPP mode as addressstrobe. It is an active low signal.BADDR0,BADDR172,71I Base Address. These bits determine one of the four base addressesfrom which the Index and Data Registers are offset. An internal pull-down resistor of 30 KΩ is on this pin. Use a 10 KΩ resistor to pull thispin to VCC.BOUT1,BOUT271,63O UARTs Baud Output. This multi-function pin supports the associatedserial channel Baud Rate generator output signal if the test mode isselected in the Power and Test Configuration Register and the DLABbit (LCR7) is set. After the Master Reset, this pin offers the SOUTfunction.BUSY 82 I Parallel Port Busy. This pin is set high by the printer when it cannotaccept another character. It has a nominal 25 KΩ pull-down resistorattached to it.CFG0 63 I SIO Configuration Strap. These CMOS inputs select 1 of 4 defaultconfigurations in which the PC97338 powers up. An internal pull-downresistor of 30 KΩ is on this. Use a 10 KΩ resistor to pull these pins toVCC. CFG0 is multiplexed with SOUT2, BOUT2 and IRTX./CS0,/CS151, 3 O Programmable Chip Select. /CS0, 1 are programmable chip selectand/or latch enable and/or output enable signals that can be used asgame port, I/O expand, etc. The decoded address and the assertionconditions are configured via the 97338VJG’s configuration registers.